Multilayer ceramic capacitor, circuit substrate and manufacturing method of the same

Multilayer ceramic capacitor, circuit substrate and manufacturing method of the same

A multilayer ceramic capacitor includes: a ceramic multilayer structure having a structure in which each of ceramic dielectric layers and each of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the ceramic multilayer structure, a main phase of the p...

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Hauptverfasser: Oshima, Michio, Shibata, Yoshinori, Yanagisawa, Atsuhiro, Moteki, Hiroyuki, Iwai, Daisuke
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
CAPACITORS
CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
ELECTRICITY
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creator Oshima, Michio
Shibata, Yoshinori
Yanagisawa, Atsuhiro
Moteki, Hiroyuki
Iwai, Daisuke
description A multilayer ceramic capacitor includes: a ceramic multilayer structure having a structure in which each of ceramic dielectric layers and each of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the ceramic multilayer structure, a main phase of the plurality of ceramic dielectric layers having a perovskite structure that includes Ca and Zr and is expressed by a general formula ABO3; and a pair of external electrodes that are formed on the two edge faces, wherein 300×TE/TA−12≤30 is satisfied when a volume TA is a length CL×a width CW×a thickness CT of the ceramic multilayer structure and a volume TE is a length EL×a width EW×a thickness ET×a stacked number of the plurality of internal electrode layers in a capacity region.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11004605B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11004605B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11004605B23</originalsourceid><addsrcrecordid>eNqNzDsOwjAMgOEsDAi4g9lBSnkdAARiYaLMlXEdaimPKnEGbg8DB2D6l0__1LS36lU8vjkDccYgBIQjkmjKKyDJVEWh1GfRjMqAsYeAsTokrVniCwLrkHpIDnRgKBh4biYOfeHFrzOzvJzb03XNY-q4fO8cWbvHvWms3R3s_rjZ_mM-y_05Iw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Multilayer ceramic capacitor, circuit substrate and manufacturing method of the same</title><source>esp@cenet</source><creator>Oshima, Michio ; Shibata, Yoshinori ; Yanagisawa, Atsuhiro ; Moteki, Hiroyuki ; Iwai, Daisuke</creator><creatorcontrib>Oshima, Michio ; Shibata, Yoshinori ; Yanagisawa, Atsuhiro ; Moteki, Hiroyuki ; Iwai, Daisuke</creatorcontrib><description>A multilayer ceramic capacitor includes: a ceramic multilayer structure having a structure in which each of ceramic dielectric layers and each of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the ceramic multilayer structure, a main phase of the plurality of ceramic dielectric layers having a perovskite structure that includes Ca and Zr and is expressed by a general formula ABO3; and a pair of external electrodes that are formed on the two edge faces, wherein 300×TE/TA−12≤30 is satisfied when a volume TA is a length CL×a width CW×a thickness CT of the ceramic multilayer structure and a volume TE is a length EL×a width EW×a thickness ET×a stacked number of the plurality of internal electrode layers in a capacity region.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CAPACITORS ; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE ; ELECTRICITY</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210511&amp;DB=EPODOC&amp;CC=US&amp;NR=11004605B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210511&amp;DB=EPODOC&amp;CC=US&amp;NR=11004605B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Oshima, Michio</creatorcontrib><creatorcontrib>Shibata, Yoshinori</creatorcontrib><creatorcontrib>Yanagisawa, Atsuhiro</creatorcontrib><creatorcontrib>Moteki, Hiroyuki</creatorcontrib><creatorcontrib>Iwai, Daisuke</creatorcontrib><title>Multilayer ceramic capacitor, circuit substrate and manufacturing method of the same</title><description>A multilayer ceramic capacitor includes: a ceramic multilayer structure having a structure in which each of ceramic dielectric layers and each of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the ceramic multilayer structure, a main phase of the plurality of ceramic dielectric layers having a perovskite structure that includes Ca and Zr and is expressed by a general formula ABO3; and a pair of external electrodes that are formed on the two edge faces, wherein 300×TE/TA−12≤30 is satisfied when a volume TA is a length CL×a width CW×a thickness CT of the ceramic multilayer structure and a volume TE is a length EL×a width EW×a thickness ET×a stacked number of the plurality of internal electrode layers in a capacity region.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CAPACITORS</subject><subject>CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzDsOwjAMgOEsDAi4g9lBSnkdAARiYaLMlXEdaimPKnEGbg8DB2D6l0__1LS36lU8vjkDccYgBIQjkmjKKyDJVEWh1GfRjMqAsYeAsTokrVniCwLrkHpIDnRgKBh4biYOfeHFrzOzvJzb03XNY-q4fO8cWbvHvWms3R3s_rjZ_mM-y_05Iw</recordid><startdate>20210511</startdate><enddate>20210511</enddate><creator>Oshima, Michio</creator><creator>Shibata, Yoshinori</creator><creator>Yanagisawa, Atsuhiro</creator><creator>Moteki, Hiroyuki</creator><creator>Iwai, Daisuke</creator><scope>EVB</scope></search><sort><creationdate>20210511</creationdate><title>Multilayer ceramic capacitor, circuit substrate and manufacturing method of the same</title><author>Oshima, Michio ; Shibata, Yoshinori ; Yanagisawa, Atsuhiro ; Moteki, Hiroyuki ; Iwai, Daisuke</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11004605B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CAPACITORS</topic><topic>CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>Oshima, Michio</creatorcontrib><creatorcontrib>Shibata, Yoshinori</creatorcontrib><creatorcontrib>Yanagisawa, Atsuhiro</creatorcontrib><creatorcontrib>Moteki, Hiroyuki</creatorcontrib><creatorcontrib>Iwai, Daisuke</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Oshima, Michio</au><au>Shibata, Yoshinori</au><au>Yanagisawa, Atsuhiro</au><au>Moteki, Hiroyuki</au><au>Iwai, Daisuke</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Multilayer ceramic capacitor, circuit substrate and manufacturing method of the same</title><date>2021-05-11</date><risdate>2021</risdate><abstract>A multilayer ceramic capacitor includes: a ceramic multilayer structure having a structure in which each of ceramic dielectric layers and each of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the ceramic multilayer structure, a main phase of the plurality of ceramic dielectric layers having a perovskite structure that includes Ca and Zr and is expressed by a general formula ABO3; and a pair of external electrodes that are formed on the two edge faces, wherein 300×TE/TA−12≤30 is satisfied when a volume TA is a length CL×a width CW×a thickness CT of the ceramic multilayer structure and a volume TE is a length EL×a width EW×a thickness ET×a stacked number of the plurality of internal electrode layers in a capacity region.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
CAPACITORS
CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
ELECTRICITY
title Multilayer ceramic capacitor, circuit substrate and manufacturing method of the same
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T15%3A36%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Oshima,%20Michio&rft.date=2021-05-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11004605B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true