Enabling high speed command address interface for random read

A memory device includes a memory controller to transmit or receive input/output ("I/O") data via an I/O signal, as well as transmit command data, address data, or parameter data via another signal in parallel with transmitting or receiving the I/O data. The memory device also includes a m...

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Hauptverfasser:	Ghatawade, Vinayak, Bhatia, Sneha
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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creator	Ghatawade, Vinayak Bhatia, Sneha
description	A memory device includes a memory controller to transmit or receive input/output ("I/O") data via an I/O signal, as well as transmit command data, address data, or parameter data via another signal in parallel with transmitting or receiving the I/O data. The memory device also includes a memory module communicably coupled to the memory controller. The memory module receives the command data, address data, or parameter data from the memory controller to perform an operation.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
title	Enabling high speed command address interface for random read
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