Butted body contact for SOI transistor
Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is "off" (Vg approximately 0 volts). When the transistor is "on" (Vg>Vt), the re...
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creator | Willard, Simon Edward |
description | Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is "off" (Vg approximately 0 volts). When the transistor is "on" (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10985183B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10985183B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10985183B23</originalsourceid><addsrcrecordid>eNrjZFBzKi0pSU1RSMpPqVRIzs8rSUwuUUjLL1II9vdUKClKzCvOLC7JL-JhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYYGlhamhhbGTkbGxKgBAFHeJ3Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Butted body contact for SOI transistor</title><source>esp@cenet</source><creator>Willard, Simon Edward</creator><creatorcontrib>Willard, Simon Edward</creatorcontrib><description>Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is "off" (Vg approximately 0 volts). When the transistor is "on" (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.</description><language>eng</language><subject>AMPLIFIERS ; BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210420&DB=EPODOC&CC=US&NR=10985183B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210420&DB=EPODOC&CC=US&NR=10985183B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Willard, Simon Edward</creatorcontrib><title>Butted body contact for SOI transistor</title><description>Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is "off" (Vg approximately 0 volts). When the transistor is "on" (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.</description><subject>AMPLIFIERS</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBzKi0pSU1RSMpPqVRIzs8rSUwuUUjLL1II9vdUKClKzCvOLC7JL-JhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYYGlhamhhbGTkbGxKgBAFHeJ3Q</recordid><startdate>20210420</startdate><enddate>20210420</enddate><creator>Willard, Simon Edward</creator><scope>EVB</scope></search><sort><creationdate>20210420</creationdate><title>Butted body contact for SOI transistor</title><author>Willard, Simon Edward</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10985183B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>AMPLIFIERS</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Willard, Simon Edward</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Willard, Simon Edward</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Butted body contact for SOI transistor</title><date>2021-04-20</date><risdate>2021</risdate><abstract>Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is "off" (Vg approximately 0 volts). When the transistor is "on" (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | AMPLIFIERS BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Butted body contact for SOI transistor |
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