Packed data element predication processors, methods, systems, and instructions
A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to de...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Singhal, Ronak Toll, Bret L Guy, Buford M Naik, Mishali |
description | A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10963257B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10963257B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10963257B23</originalsourceid><addsrcrecordid>eNqNyr0KwjAUhuEsDqLeQ9wVtMVKV0VxEkGdyyH5xNDmh5zj4N0bwQtwep_hHavzhUwPqy0JaQzwCKJThnWGxMVQHA2YY-aF9pBntAX8ZoEvoGC1Cyz5Zb43T9XoQQNj9utEzY-H2_60RIodOJFBgHT363rVNnW12e6q-p_nAzmENxQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Packed data element predication processors, methods, systems, and instructions</title><source>esp@cenet</source><creator>Singhal, Ronak ; Toll, Bret L ; Guy, Buford M ; Naik, Mishali</creator><creatorcontrib>Singhal, Ronak ; Toll, Bret L ; Guy, Buford M ; Naik, Mishali</creatorcontrib><description>A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210330&DB=EPODOC&CC=US&NR=10963257B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210330&DB=EPODOC&CC=US&NR=10963257B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Singhal, Ronak</creatorcontrib><creatorcontrib>Toll, Bret L</creatorcontrib><creatorcontrib>Guy, Buford M</creatorcontrib><creatorcontrib>Naik, Mishali</creatorcontrib><title>Packed data element predication processors, methods, systems, and instructions</title><description>A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyr0KwjAUhuEsDqLeQ9wVtMVKV0VxEkGdyyH5xNDmh5zj4N0bwQtwep_hHavzhUwPqy0JaQzwCKJThnWGxMVQHA2YY-aF9pBntAX8ZoEvoGC1Cyz5Zb43T9XoQQNj9utEzY-H2_60RIodOJFBgHT363rVNnW12e6q-p_nAzmENxQ</recordid><startdate>20210330</startdate><enddate>20210330</enddate><creator>Singhal, Ronak</creator><creator>Toll, Bret L</creator><creator>Guy, Buford M</creator><creator>Naik, Mishali</creator><scope>EVB</scope></search><sort><creationdate>20210330</creationdate><title>Packed data element predication processors, methods, systems, and instructions</title><author>Singhal, Ronak ; Toll, Bret L ; Guy, Buford M ; Naik, Mishali</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10963257B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Singhal, Ronak</creatorcontrib><creatorcontrib>Toll, Bret L</creatorcontrib><creatorcontrib>Guy, Buford M</creatorcontrib><creatorcontrib>Naik, Mishali</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Singhal, Ronak</au><au>Toll, Bret L</au><au>Guy, Buford M</au><au>Naik, Mishali</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Packed data element predication processors, methods, systems, and instructions</title><date>2021-03-30</date><risdate>2021</risdate><abstract>A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US10963257B2 |
source | esp@cenet |
subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Packed data element predication processors, methods, systems, and instructions |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-19T23%3A37%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Singhal,%20Ronak&rft.date=2021-03-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10963257B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |