Manufacturing method of semiconductor device including conductive structure
A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/...
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creator | Hsu, Te-Chang Huang, Chun-Jen Lin, Che-Hsien Huang, Cheng-Yeh Wang, Yao-Jhan Su, Yu-Chih |
description | A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10957762B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10957762B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10957762B23</originalsourceid><addsrcrecordid>eNrjZPD2TcwrTUtMLiktysxLV8hNLcnIT1HIT1MoTs3NTM7PSylNLskvUkhJLctMTlXIzEvOKU0BKYRKZZalKhSXFJWC9KfyMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjU4oLE5NS81JL40GBDA0tTc3MzIycjY2LUAADpojbL</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Manufacturing method of semiconductor device including conductive structure</title><source>esp@cenet</source><creator>Hsu, Te-Chang ; Huang, Chun-Jen ; Lin, Che-Hsien ; Huang, Cheng-Yeh ; Wang, Yao-Jhan ; Su, Yu-Chih</creator><creatorcontrib>Hsu, Te-Chang ; Huang, Chun-Jen ; Lin, Che-Hsien ; Huang, Cheng-Yeh ; Wang, Yao-Jhan ; Su, Yu-Chih</creatorcontrib><description>A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210323&DB=EPODOC&CC=US&NR=10957762B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210323&DB=EPODOC&CC=US&NR=10957762B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hsu, Te-Chang</creatorcontrib><creatorcontrib>Huang, Chun-Jen</creatorcontrib><creatorcontrib>Lin, Che-Hsien</creatorcontrib><creatorcontrib>Huang, Cheng-Yeh</creatorcontrib><creatorcontrib>Wang, Yao-Jhan</creatorcontrib><creatorcontrib>Su, Yu-Chih</creatorcontrib><title>Manufacturing method of semiconductor device including conductive structure</title><description>A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPD2TcwrTUtMLiktysxLV8hNLcnIT1HIT1MoTs3NTM7PSylNLskvUkhJLctMTlXIzEvOKU0BKYRKZZalKhSXFJWC9KfyMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjU4oLE5NS81JL40GBDA0tTc3MzIycjY2LUAADpojbL</recordid><startdate>20210323</startdate><enddate>20210323</enddate><creator>Hsu, Te-Chang</creator><creator>Huang, Chun-Jen</creator><creator>Lin, Che-Hsien</creator><creator>Huang, Cheng-Yeh</creator><creator>Wang, Yao-Jhan</creator><creator>Su, Yu-Chih</creator><scope>EVB</scope></search><sort><creationdate>20210323</creationdate><title>Manufacturing method of semiconductor device including conductive structure</title><author>Hsu, Te-Chang ; Huang, Chun-Jen ; Lin, Che-Hsien ; Huang, Cheng-Yeh ; Wang, Yao-Jhan ; Su, Yu-Chih</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10957762B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Hsu, Te-Chang</creatorcontrib><creatorcontrib>Huang, Chun-Jen</creatorcontrib><creatorcontrib>Lin, Che-Hsien</creatorcontrib><creatorcontrib>Huang, Cheng-Yeh</creatorcontrib><creatorcontrib>Wang, Yao-Jhan</creatorcontrib><creatorcontrib>Su, Yu-Chih</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hsu, Te-Chang</au><au>Huang, Chun-Jen</au><au>Lin, Che-Hsien</au><au>Huang, Cheng-Yeh</au><au>Wang, Yao-Jhan</au><au>Su, Yu-Chih</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Manufacturing method of semiconductor device including conductive structure</title><date>2021-03-23</date><risdate>2021</risdate><abstract>A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Manufacturing method of semiconductor device including conductive structure |
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