Staggered die stacking across heterogeneous modules

An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and t...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Chew, Yen Hsiang
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Chew, Yen Hsiang
description An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10943887B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10943887B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10943887B23</originalsourceid><addsrcrecordid>eNrjZDAOLklMT08tSk1RSMlMVSguSUzOzsxLV0hMLsovLlbISC1JLcpPT81LzS8tVsjNTynNSS3mYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyUD1JfGhwYYGlibGFhbmTkbGxKgBAC0yLRs</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Staggered die stacking across heterogeneous modules</title><source>esp@cenet</source><creator>Chew, Yen Hsiang</creator><creatorcontrib>Chew, Yen Hsiang</creatorcontrib><description>An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210309&amp;DB=EPODOC&amp;CC=US&amp;NR=10943887B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210309&amp;DB=EPODOC&amp;CC=US&amp;NR=10943887B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chew, Yen Hsiang</creatorcontrib><title>Staggered die stacking across heterogeneous modules</title><description>An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAOLklMT08tSk1RSMlMVSguSUzOzsxLV0hMLsovLlbISC1JLcpPT81LzS8tVsjNTynNSS3mYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyUD1JfGhwYYGlibGFhbmTkbGxKgBAC0yLRs</recordid><startdate>20210309</startdate><enddate>20210309</enddate><creator>Chew, Yen Hsiang</creator><scope>EVB</scope></search><sort><creationdate>20210309</creationdate><title>Staggered die stacking across heterogeneous modules</title><author>Chew, Yen Hsiang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10943887B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Chew, Yen Hsiang</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chew, Yen Hsiang</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Staggered die stacking across heterogeneous modules</title><date>2021-03-09</date><risdate>2021</risdate><abstract>An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US10943887B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Staggered die stacking across heterogeneous modules
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-11T20%3A34%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Chew,%20Yen%20Hsiang&rft.date=2021-03-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10943887B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true