Minimizing shorting between FinFET epitaxial regions

The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate struct...

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Bibliographische Detailangaben

Hauptverfasser:	Pranatharthiharan, Balasubramanian, Cheng, Kangguo, Reznicek, Alexander, Surisetty, Charan V
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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