Delay-locked loop, memory device, and method for operating delay-locked loop

A delay-locked loop circuit includes a delay line and a control unit. The delay line functions to delay an input signal to generate a first delay signal. The control unit receives the input signal, an access start signal and an access end signal, and functions to generate a control signal according...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
1. Verfasser:	Chang, Chuan-Jen
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	Chang, Chuan-Jen
description	A delay-locked loop circuit includes a delay line and a control unit. The delay line functions to delay an input signal to generate a first delay signal. The control unit receives the input signal, an access start signal and an access end signal, and functions to generate a control signal according to the input signal, the access start signal and the access end signal, wherein the control signal functions to control the delay line between two read operations.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10923177B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10923177B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10923177B13</originalsourceid><addsrcrecordid>eNrjZPBxSc1JrNTNyU_OTk1RyMnPL9BRyE3NzS-qVEhJLctMTtVRSMxLAQqVZOSnKKTlFynkF6QWJZZk5qUDFaBp5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgaWRsaG5uZOhsbEqAEARnc1Vg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Delay-locked loop, memory device, and method for operating delay-locked loop</title><source>esp@cenet</source><creator>Chang, Chuan-Jen</creator><creatorcontrib>Chang, Chuan-Jen</creatorcontrib><description>A delay-locked loop circuit includes a delay line and a control unit. The delay line functions to delay an input signal to generate a first delay signal. The control unit receives the input signal, an access start signal and an access end signal, and functions to generate a control signal according to the input signal, the access start signal and the access end signal, wherein the control signal functions to control the delay line between two read operations.</description><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210216&DB=EPODOC&CC=US&NR=10923177B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210216&DB=EPODOC&CC=US&NR=10923177B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chang, Chuan-Jen</creatorcontrib><title>Delay-locked loop, memory device, and method for operating delay-locked loop</title><description>A delay-locked loop circuit includes a delay line and a control unit. The delay line functions to delay an input signal to generate a first delay signal. The control unit receives the input signal, an access start signal and an access end signal, and functions to generate a control signal according to the input signal, the access start signal and the access end signal, wherein the control signal functions to control the delay line between two read operations.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPBxSc1JrNTNyU_OTk1RyMnPL9BRyE3NzS-qVEhJLctMTtVRSMxLAQqVZOSnKKTlFynkF6QWJZZk5qUDFaBp5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgaWRsaG5uZOhsbEqAEARnc1Vg</recordid><startdate>20210216</startdate><enddate>20210216</enddate><creator>Chang, Chuan-Jen</creator><scope>EVB</scope></search><sort><creationdate>20210216</creationdate><title>Delay-locked loop, memory device, and method for operating delay-locked loop</title><author>Chang, Chuan-Jen</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10923177B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Chang, Chuan-Jen</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chang, Chuan-Jen</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Delay-locked loop, memory device, and method for operating delay-locked loop</title><date>2021-02-16</date><risdate>2021</risdate><abstract>A delay-locked loop circuit includes a delay line and a control unit. The delay line functions to delay an input signal to generate a first delay signal. The control unit receives the input signal, an access start signal and an access end signal, and functions to generate a control signal according to the input signal, the access start signal and the access end signal, wherein the control signal functions to control the delay line between two read operations.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US10923177B1
source	esp@cenet
subjects	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
title	Delay-locked loop, memory device, and method for operating delay-locked loop
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T01%3A54%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Chang,%20Chuan-Jen&rft.date=2021-02-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10923177B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true