Genealogy driven IC layout generator and classification method

Genealogy driven IC layout generator and classification method

Systems and methods for systems and methods for generating the complete set of IC design layout clips, or any part of the complete set, satisfying usefulness criteria and of a prespecified size. A method includes generating an initial set of integrated circuit (IC) design layout clips as a current s...

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Hauptverfasser: Madkour, Kareem, Hammouda, Sherif Ahmed Abdel-Wahab, Sabry, Mohamed-Nabil
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator Madkour, Kareem
Hammouda, Sherif Ahmed Abdel-Wahab
Sabry, Mohamed-Nabil
description Systems and methods for systems and methods for generating the complete set of IC design layout clips, or any part of the complete set, satisfying usefulness criteria and of a prespecified size. A method includes generating an initial set of integrated circuit (IC) design layout clips as a current set of IC design layout clips. The method includes removing any of IC design layout clips from the current set of IC design layout clips that do not meet the one or more usefulness criteria. The method includes, while a size of the IC design layout clips is less than a desired clip size, generating a new set of IC design layout clips from the current set of IC design layout clips according to every combination of pairs of the design layout clips in the current set of IC design layout clips, and repeating the removing process. The method includes, when the size of the IC design layout clips is not less than the desired clip size, storing the current set of IC design layout clips as a final set of IC design layout clips.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Genealogy driven IC layout generator and classification method
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