Memory interface latch with integrated write-through and fence functions
A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Gerhard, Elizabeth L Adams, Chad A Christensen, Todd A Freiburger, Peter T |
| description | A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10916323B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10916323B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10916323B23</originalsourceid><addsrcrecordid>eNrjZPDwTc3NL6pUyMwrSS1KS0xOVchJLEnOUCjPLMkAC6YXJZakpiiUF2WWpOqWZBTll6ZnKCTmpSikpeYBVaeV5iWXZObnFfMwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTiAqDReakl8aHBhgaWhmbGRsZORsbEqAEA2Hk01A</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Memory interface latch with integrated write-through and fence functions</title><source>esp@cenet</source><creator>Gerhard, Elizabeth L ; Adams, Chad A ; Christensen, Todd A ; Freiburger, Peter T</creator><creatorcontrib>Gerhard, Elizabeth L ; Adams, Chad A ; Christensen, Todd A ; Freiburger, Peter T</creatorcontrib><description>A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; STATIC STORES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210209&DB=EPODOC&CC=US&NR=10916323B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,782,887,25573,76557</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210209&DB=EPODOC&CC=US&NR=10916323B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Gerhard, Elizabeth L</creatorcontrib><creatorcontrib>Adams, Chad A</creatorcontrib><creatorcontrib>Christensen, Todd A</creatorcontrib><creatorcontrib>Freiburger, Peter T</creatorcontrib><title>Memory interface latch with integrated write-through and fence functions</title><description>A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPDwTc3NL6pUyMwrSS1KS0xOVchJLEnOUCjPLMkAC6YXJZakpiiUF2WWpOqWZBTll6ZnKCTmpSikpeYBVaeV5iWXZObnFfMwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTiAqDReakl8aHBhgaWhmbGRsZORsbEqAEA2Hk01A</recordid><startdate>20210209</startdate><enddate>20210209</enddate><creator>Gerhard, Elizabeth L</creator><creator>Adams, Chad A</creator><creator>Christensen, Todd A</creator><creator>Freiburger, Peter T</creator><scope>EVB</scope></search><sort><creationdate>20210209</creationdate><title>Memory interface latch with integrated write-through and fence functions</title><author>Gerhard, Elizabeth L ; Adams, Chad A ; Christensen, Todd A ; Freiburger, Peter T</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10916323B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Gerhard, Elizabeth L</creatorcontrib><creatorcontrib>Adams, Chad A</creatorcontrib><creatorcontrib>Christensen, Todd A</creatorcontrib><creatorcontrib>Freiburger, Peter T</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gerhard, Elizabeth L</au><au>Adams, Chad A</au><au>Christensen, Todd A</au><au>Freiburger, Peter T</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Memory interface latch with integrated write-through and fence functions</title><date>2021-02-09</date><risdate>2021</risdate><abstract>A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US10916323B2 |
| source | esp@cenet |
| subjects | BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES |
| title | Memory interface latch with integrated write-through and fence functions |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-11-30T05%3A26%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Gerhard,%20Elizabeth%20L&rft.date=2021-02-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10916323B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |