Method of manufacturing a semiconductor package

Method of manufacturing a semiconductor package

In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devic...

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Hauptverfasser: Han, Won-Gil, Yoo, Se-Jin, Joo, Hong-Sub
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator Han, Won-Gil
Yoo, Se-Jin
Joo, Hong-Sub
description In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10903177B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10903177B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10903177B23</originalsourceid><addsrcrecordid>eNrjZND3TS3JyE9RyE9TyE3MK01LTC4pLcrMS1dIVChOzc1Mzs9LKU0uyS9SKEhMzk5MT-VhYE1LzClO5YXS3AyKbq4hzh66qQX58anFQFWpeakl8aHBhgaWBsaG5uZORsbEqAEAPe0rOA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of manufacturing a semiconductor package</title><source>esp@cenet</source><creator>Han, Won-Gil ; Yoo, Se-Jin ; Joo, Hong-Sub</creator><creatorcontrib>Han, Won-Gil ; Yoo, Se-Jin ; Joo, Hong-Sub</creatorcontrib><description>In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210126&amp;DB=EPODOC&amp;CC=US&amp;NR=10903177B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210126&amp;DB=EPODOC&amp;CC=US&amp;NR=10903177B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Han, Won-Gil</creatorcontrib><creatorcontrib>Yoo, Se-Jin</creatorcontrib><creatorcontrib>Joo, Hong-Sub</creatorcontrib><title>Method of manufacturing a semiconductor package</title><description>In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND3TS3JyE9RyE9TyE3MK01LTC4pLcrMS1dIVChOzc1Mzs9LKU0uyS9SKEhMzk5MT-VhYE1LzClO5YXS3AyKbq4hzh66qQX58anFQFWpeakl8aHBhgaWBsaG5uZORsbEqAEAPe0rOA</recordid><startdate>20210126</startdate><enddate>20210126</enddate><creator>Han, Won-Gil</creator><creator>Yoo, Se-Jin</creator><creator>Joo, Hong-Sub</creator><scope>EVB</scope></search><sort><creationdate>20210126</creationdate><title>Method of manufacturing a semiconductor package</title><author>Han, Won-Gil ; Yoo, Se-Jin ; Joo, Hong-Sub</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10903177B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Han, Won-Gil</creatorcontrib><creatorcontrib>Yoo, Se-Jin</creatorcontrib><creatorcontrib>Joo, Hong-Sub</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Han, Won-Gil</au><au>Yoo, Se-Jin</au><au>Joo, Hong-Sub</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of manufacturing a semiconductor package</title><date>2021-01-26</date><risdate>2021</risdate><abstract>In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method of manufacturing a semiconductor package
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-29T01%3A04%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Han,%20Won-Gil&rft.date=2021-01-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10903177B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true