Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions

A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality o...

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Hauptverfasser: Yen, Luke, Eibl, Patrick, Stempel, Brian Michael, McAvoy, William James, Ghoshal, Pritha, Choudhary, Niket, Speier, Thomas Philip
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creator Yen, Luke
Eibl, Patrick
Stempel, Brian Michael
McAvoy, William James
Ghoshal, Pritha
Choudhary, Niket
Speier, Thomas Philip
description A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10877895B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10877895B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10877895B23</originalsourceid><addsrcrecordid>eNqNir0KAjEQBq-xEPUd1l7BH-TOVlFsrNT6WHJfTOBMQnZP9O09xAewmZlihkVzhrrYzIhT4szaSZ-hIXmL4kE2ZkoZFmqcD3fCy7Sd-CfIsHE9o0NGMCBRVnx_0ZhBPojmzqiPQcbFwHIrmPw8KqbHw3V_miPFGpLYIEDr22W5qMqy2m52q_U_zwcICD-T</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions</title><source>esp@cenet</source><creator>Yen, Luke ; Eibl, Patrick ; Stempel, Brian Michael ; McAvoy, William James ; Ghoshal, Pritha ; Choudhary, Niket ; Speier, Thomas Philip</creator><creatorcontrib>Yen, Luke ; Eibl, Patrick ; Stempel, Brian Michael ; McAvoy, William James ; Ghoshal, Pritha ; Choudhary, Niket ; Speier, Thomas Philip</creatorcontrib><description>A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20201229&amp;DB=EPODOC&amp;CC=US&amp;NR=10877895B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20201229&amp;DB=EPODOC&amp;CC=US&amp;NR=10877895B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Yen, Luke</creatorcontrib><creatorcontrib>Eibl, Patrick</creatorcontrib><creatorcontrib>Stempel, Brian Michael</creatorcontrib><creatorcontrib>McAvoy, William James</creatorcontrib><creatorcontrib>Ghoshal, Pritha</creatorcontrib><creatorcontrib>Choudhary, Niket</creatorcontrib><creatorcontrib>Speier, Thomas Philip</creatorcontrib><title>Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions</title><description>A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNir0KAjEQBq-xEPUd1l7BH-TOVlFsrNT6WHJfTOBMQnZP9O09xAewmZlihkVzhrrYzIhT4szaSZ-hIXmL4kE2ZkoZFmqcD3fCy7Sd-CfIsHE9o0NGMCBRVnx_0ZhBPojmzqiPQcbFwHIrmPw8KqbHw3V_miPFGpLYIEDr22W5qMqy2m52q_U_zwcICD-T</recordid><startdate>20201229</startdate><enddate>20201229</enddate><creator>Yen, Luke</creator><creator>Eibl, Patrick</creator><creator>Stempel, Brian Michael</creator><creator>McAvoy, William James</creator><creator>Ghoshal, Pritha</creator><creator>Choudhary, Niket</creator><creator>Speier, Thomas Philip</creator><scope>EVB</scope></search><sort><creationdate>20201229</creationdate><title>Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions</title><author>Yen, Luke ; Eibl, Patrick ; Stempel, Brian Michael ; McAvoy, William James ; Ghoshal, Pritha ; Choudhary, Niket ; Speier, Thomas Philip</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10877895B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Yen, Luke</creatorcontrib><creatorcontrib>Eibl, Patrick</creatorcontrib><creatorcontrib>Stempel, Brian Michael</creatorcontrib><creatorcontrib>McAvoy, William James</creatorcontrib><creatorcontrib>Ghoshal, Pritha</creatorcontrib><creatorcontrib>Choudhary, Niket</creatorcontrib><creatorcontrib>Speier, Thomas Philip</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yen, Luke</au><au>Eibl, Patrick</au><au>Stempel, Brian Michael</au><au>McAvoy, William James</au><au>Ghoshal, Pritha</au><au>Choudhary, Niket</au><au>Speier, Thomas Philip</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions</title><date>2020-12-29</date><risdate>2020</risdate><abstract>A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.</abstract><oa>free_for_read</oa></addata></record>
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source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-04T22%3A42%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Yen,%20Luke&rft.date=2020-12-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10877895B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true