Adjustable performance boot system

An adjustable performance boot system includes a processing system and an SPI memory storing firmware volumes. The processing system retrieves, via an SPI interface at a first SPI interface performance level, a first firmware volume including a first hash value generated using a second firmware volu...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Luong, Anh Dinh, Cheng, Po-Yu, Diaz, Juan Francisco
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Luong, Anh Dinh
Cheng, Po-Yu
Diaz, Juan Francisco
description An adjustable performance boot system includes a processing system and an SPI memory storing firmware volumes. The processing system retrieves, via an SPI interface at a first SPI interface performance level, a first firmware volume including a first hash value generated using a second firmware volume. The processing system then increases the SPI interface performance level, retrieves the second firmware volume via the SPI interface at the increased SPI interface performance level, generates a second hash value using that second firmware volume and, in response to it not matching the first hash value, lowers the SPI interface performance level. The processing system then retrieves the second firmware volume via the SPI interface at the decreased SPI interface performance level, generates a third hash value using that second firmware volume and, in response to it matching the first hash value, uses that second firmware volume to provide a BIOS.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10853085B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10853085B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10853085B23</originalsourceid><addsrcrecordid>eNrjZFByTMkqLS5JTMpJVShILUrLL8pNzEtOVUjKzy9RKK4sLknN5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgYWpsZA7GRkTIwaANarJoM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Adjustable performance boot system</title><source>esp@cenet</source><creator>Luong, Anh Dinh ; Cheng, Po-Yu ; Diaz, Juan Francisco</creator><creatorcontrib>Luong, Anh Dinh ; Cheng, Po-Yu ; Diaz, Juan Francisco</creatorcontrib><description>An adjustable performance boot system includes a processing system and an SPI memory storing firmware volumes. The processing system retrieves, via an SPI interface at a first SPI interface performance level, a first firmware volume including a first hash value generated using a second firmware volume. The processing system then increases the SPI interface performance level, retrieves the second firmware volume via the SPI interface at the increased SPI interface performance level, generates a second hash value using that second firmware volume and, in response to it not matching the first hash value, lowers the SPI interface performance level. The processing system then retrieves the second firmware volume via the SPI interface at the decreased SPI interface performance level, generates a third hash value using that second firmware volume and, in response to it matching the first hash value, uses that second firmware volume to provide a BIOS.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20201201&amp;DB=EPODOC&amp;CC=US&amp;NR=10853085B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20201201&amp;DB=EPODOC&amp;CC=US&amp;NR=10853085B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Luong, Anh Dinh</creatorcontrib><creatorcontrib>Cheng, Po-Yu</creatorcontrib><creatorcontrib>Diaz, Juan Francisco</creatorcontrib><title>Adjustable performance boot system</title><description>An adjustable performance boot system includes a processing system and an SPI memory storing firmware volumes. The processing system retrieves, via an SPI interface at a first SPI interface performance level, a first firmware volume including a first hash value generated using a second firmware volume. The processing system then increases the SPI interface performance level, retrieves the second firmware volume via the SPI interface at the increased SPI interface performance level, generates a second hash value using that second firmware volume and, in response to it not matching the first hash value, lowers the SPI interface performance level. The processing system then retrieves the second firmware volume via the SPI interface at the decreased SPI interface performance level, generates a third hash value using that second firmware volume and, in response to it matching the first hash value, uses that second firmware volume to provide a BIOS.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFByTMkqLS5JTMpJVShILUrLL8pNzEtOVUjKzy9RKK4sLknN5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgYWpsZA7GRkTIwaANarJoM</recordid><startdate>20201201</startdate><enddate>20201201</enddate><creator>Luong, Anh Dinh</creator><creator>Cheng, Po-Yu</creator><creator>Diaz, Juan Francisco</creator><scope>EVB</scope></search><sort><creationdate>20201201</creationdate><title>Adjustable performance boot system</title><author>Luong, Anh Dinh ; Cheng, Po-Yu ; Diaz, Juan Francisco</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10853085B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>Luong, Anh Dinh</creatorcontrib><creatorcontrib>Cheng, Po-Yu</creatorcontrib><creatorcontrib>Diaz, Juan Francisco</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Luong, Anh Dinh</au><au>Cheng, Po-Yu</au><au>Diaz, Juan Francisco</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Adjustable performance boot system</title><date>2020-12-01</date><risdate>2020</risdate><abstract>An adjustable performance boot system includes a processing system and an SPI memory storing firmware volumes. The processing system retrieves, via an SPI interface at a first SPI interface performance level, a first firmware volume including a first hash value generated using a second firmware volume. The processing system then increases the SPI interface performance level, retrieves the second firmware volume via the SPI interface at the increased SPI interface performance level, generates a second hash value using that second firmware volume and, in response to it not matching the first hash value, lowers the SPI interface performance level. The processing system then retrieves the second firmware volume via the SPI interface at the decreased SPI interface performance level, generates a third hash value using that second firmware volume and, in response to it matching the first hash value, uses that second firmware volume to provide a BIOS.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US10853085B2
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title Adjustable performance boot system
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T12%3A40%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Luong,%20Anh%20Dinh&rft.date=2020-12-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10853085B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true