Mask pattern correction system, and semiconductor device manufacturing method utilizing said correction system

According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Uno, Taiga, Shiraishi, Kenji, Ichikawa, Hirotaka, Takeuchi, Yuto, Miyairi, Masahiro, Ito, Sachiyo, Yoshimura, Hiroshi, Hino, Kazuyuki, Mashita, Hiromitsu, Ooki, Shinichirou
Format:	Patent
Sprache:	eng
Schlagworte:	APPARATUS SPECIALLY ADAPTED THEREFOR CALCULATING CINEMATOGRAPHY COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTROGRAPHY HOLOGRAPHY MATERIALS THEREFOR ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS
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