Gate structure and method with enhanced gate contact and threshold voltage

The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrat...

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Bibliographische Detailangaben
Hauptverfasser: Peng, Yen-Ming, Ho, Wei-Shuo, Liu, Max
Format: Patent
Sprache:eng
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