Layout of a memory cell of an integrated circuit

Techniques for generating a layout of a multi-port memory cell are provided. A specification describing at least on port within a memory cell is defined. A base memory cell including at least one extension point is modeled. A port that interfaces with the base memory cell is identified from the spec...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Sautter, Rolf, Rozenfeld, Amira, Kalyanasundaram, Shankar, Veerabhadraiah, Rajesh, Darla, Ananth Nag Raja
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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