Gate cut first isolation formation with contact forming process mask protection
A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed...
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creator | Tabakman, Keith H Yang, Xiaoming Chee, Jeffrey Gu, Sipeng |
description | A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10825811B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10825811B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10825811B23</originalsourceid><addsrcrecordid>eNrjZPB3TyxJVUguLVFIyywqLlHILM7PSSzJzM9TSMsvyoWwyjNLMhSS8_NKEpNLwMKZeekKBUX5yanFxQq5icXZIE5JajJIMQ8Da1piTnEqL5TmZlB0cw1x9tBNLciPTy0uSExOzUstiQ8NNjSwMDK1MDR0MjImRg0ApAw3wA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Gate cut first isolation formation with contact forming process mask protection</title><source>esp@cenet</source><creator>Tabakman, Keith H ; Yang, Xiaoming ; Chee, Jeffrey ; Gu, Sipeng</creator><creatorcontrib>Tabakman, Keith H ; Yang, Xiaoming ; Chee, Jeffrey ; Gu, Sipeng</creatorcontrib><description>A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201103&DB=EPODOC&CC=US&NR=10825811B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201103&DB=EPODOC&CC=US&NR=10825811B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Tabakman, Keith H</creatorcontrib><creatorcontrib>Yang, Xiaoming</creatorcontrib><creatorcontrib>Chee, Jeffrey</creatorcontrib><creatorcontrib>Gu, Sipeng</creatorcontrib><title>Gate cut first isolation formation with contact forming process mask protection</title><description>A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPB3TyxJVUguLVFIyywqLlHILM7PSSzJzM9TSMsvyoWwyjNLMhSS8_NKEpNLwMKZeekKBUX5yanFxQq5icXZIE5JajJIMQ8Da1piTnEqL5TmZlB0cw1x9tBNLciPTy0uSExOzUstiQ8NNjSwMDK1MDR0MjImRg0ApAw3wA</recordid><startdate>20201103</startdate><enddate>20201103</enddate><creator>Tabakman, Keith H</creator><creator>Yang, Xiaoming</creator><creator>Chee, Jeffrey</creator><creator>Gu, Sipeng</creator><scope>EVB</scope></search><sort><creationdate>20201103</creationdate><title>Gate cut first isolation formation with contact forming process mask protection</title><author>Tabakman, Keith H ; Yang, Xiaoming ; Chee, Jeffrey ; Gu, Sipeng</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10825811B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Tabakman, Keith H</creatorcontrib><creatorcontrib>Yang, Xiaoming</creatorcontrib><creatorcontrib>Chee, Jeffrey</creatorcontrib><creatorcontrib>Gu, Sipeng</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tabakman, Keith H</au><au>Yang, Xiaoming</au><au>Chee, Jeffrey</au><au>Gu, Sipeng</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Gate cut first isolation formation with contact forming process mask protection</title><date>2020-11-03</date><risdate>2020</risdate><abstract>A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Gate cut first isolation formation with contact forming process mask protection |
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