State machine controlling power transistor through fault and no fault

A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a cond...

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Hauptverfasser:	Nortman, Stephen, Aras, Sualp, Rahman, Md. Abidur, Quirk, Adam
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRICITY EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS GENERATION PULSE TECHNIQUE
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creator	Nortman, Stephen Aras, Sualp Rahman, Md. Abidur Quirk, Adam
description	A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10812063B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10812063B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10812063B23</originalsourceid><addsrcrecordid>eNrjZHANLkksSVXITUzOyMxLVUjOzyspys_JycxLVyjIL08tUigpSswrziwuyQcyM4ryS9MzFNISS3NKFBLzUhTy8iEcHgbWtMSc4lReKM3NoOjmGuLsoZtakB-fWlyQmJyal1oSHxpsaGBhaGRgZuxkZEyMGgAyVzO6</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>State machine controlling power transistor through fault and no fault</title><source>esp@cenet</source><creator>Nortman, Stephen ; Aras, Sualp ; Rahman, Md. Abidur ; Quirk, Adam</creator><creatorcontrib>Nortman, Stephen ; Aras, Sualp ; Rahman, Md. Abidur ; Quirk, Adam</creatorcontrib><description>A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ; ELECTRICITY ; EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS ; GENERATION ; PULSE TECHNIQUE</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201020&DB=EPODOC&CC=US&NR=10812063B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,782,887,25571,76555</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201020&DB=EPODOC&CC=US&NR=10812063B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Nortman, Stephen</creatorcontrib><creatorcontrib>Aras, Sualp</creatorcontrib><creatorcontrib>Rahman, Md. Abidur</creatorcontrib><creatorcontrib>Quirk, Adam</creatorcontrib><title>State machine controlling power transistor through fault and no fault</title><description>A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</subject><subject>ELECTRICITY</subject><subject>EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS</subject><subject>GENERATION</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHANLkksSVXITUzOyMxLVUjOzyspys_JycxLVyjIL08tUigpSswrziwuyQcyM4ryS9MzFNISS3NKFBLzUhTy8iEcHgbWtMSc4lReKM3NoOjmGuLsoZtakB-fWlyQmJyal1oSHxpsaGBhaGRgZuxkZEyMGgAyVzO6</recordid><startdate>20201020</startdate><enddate>20201020</enddate><creator>Nortman, Stephen</creator><creator>Aras, Sualp</creator><creator>Rahman, Md. Abidur</creator><creator>Quirk, Adam</creator><scope>EVB</scope></search><sort><creationdate>20201020</creationdate><title>State machine controlling power transistor through fault and no fault</title><author>Nortman, Stephen ; Aras, Sualp ; Rahman, Md. Abidur ; Quirk, Adam</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10812063B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</topic><topic>ELECTRICITY</topic><topic>EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS</topic><topic>GENERATION</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>Nortman, Stephen</creatorcontrib><creatorcontrib>Aras, Sualp</creatorcontrib><creatorcontrib>Rahman, Md. Abidur</creatorcontrib><creatorcontrib>Quirk, Adam</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nortman, Stephen</au><au>Aras, Sualp</au><au>Rahman, Md. Abidur</au><au>Quirk, Adam</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>State machine controlling power transistor through fault and no fault</title><date>2020-10-20</date><risdate>2020</risdate><abstract>A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.</abstract><oa>free_for_read</oa></addata></record>
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subjects	BASIC ELECTRONIC CIRCUITRY CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRICITY EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS GENERATION PULSE TECHNIQUE
title	State machine controlling power transistor through fault and no fault
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-08T08%3A14%3A08IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Nortman,%20Stephen&rft.date=2020-10-20&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10812063B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true