Semiconductor device and method of manufacturing the same
A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the f...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Choi, Jae Kwang Jeon, Kyung Yub Jeong, Soo Yeon |
description | A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10804160B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10804160B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10804160B23</originalsourceid><addsrcrecordid>eNrjZLAMTs3NTM7PSylNLskvUkhJLctMTlVIzEtRyE0tychPUchPU8hNzCtNS0wuKS3KzEtXKMlIVShOzE3lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGBhYGJoZmBk5GxsSoAQBOjC7P</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device and method of manufacturing the same</title><source>esp@cenet</source><creator>Choi, Jae Kwang ; Jeon, Kyung Yub ; Jeong, Soo Yeon</creator><creatorcontrib>Choi, Jae Kwang ; Jeon, Kyung Yub ; Jeong, Soo Yeon</creatorcontrib><description>A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201013&DB=EPODOC&CC=US&NR=10804160B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201013&DB=EPODOC&CC=US&NR=10804160B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Choi, Jae Kwang</creatorcontrib><creatorcontrib>Jeon, Kyung Yub</creatorcontrib><creatorcontrib>Jeong, Soo Yeon</creatorcontrib><title>Semiconductor device and method of manufacturing the same</title><description>A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAMTs3NTM7PSylNLskvUkhJLctMTlVIzEtRyE0tychPUchPU8hNzCtNS0wuKS3KzEtXKMlIVShOzE3lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGBhYGJoZmBk5GxsSoAQBOjC7P</recordid><startdate>20201013</startdate><enddate>20201013</enddate><creator>Choi, Jae Kwang</creator><creator>Jeon, Kyung Yub</creator><creator>Jeong, Soo Yeon</creator><scope>EVB</scope></search><sort><creationdate>20201013</creationdate><title>Semiconductor device and method of manufacturing the same</title><author>Choi, Jae Kwang ; Jeon, Kyung Yub ; Jeong, Soo Yeon</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10804160B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Choi, Jae Kwang</creatorcontrib><creatorcontrib>Jeon, Kyung Yub</creatorcontrib><creatorcontrib>Jeong, Soo Yeon</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Choi, Jae Kwang</au><au>Jeon, Kyung Yub</au><au>Jeong, Soo Yeon</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device and method of manufacturing the same</title><date>2020-10-13</date><risdate>2020</risdate><abstract>A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US10804160B2 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Semiconductor device and method of manufacturing the same |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T03%3A27%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Choi,%20Jae%20Kwang&rft.date=2020-10-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10804160B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |