Integrated circuit contact test apparatus with and method of construction
A test socket for a device under test (DUT) is disclosed in several embodiments. One embodiment shows a test socket base (16) with apertures (30) for insertion of test pin insert blocks (28). The blocks are inserted top-in or bottom-in and are provided with registration bosses 80 and teeth 92 or oth...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Erdman, Joel Sherry, Jeffrey |
| description | A test socket for a device under test (DUT) is disclosed in several embodiments. One embodiment shows a test socket base (16) with apertures (30) for insertion of test pin insert blocks (28). The blocks are inserted top-in or bottom-in and are provided with registration bosses 80 and teeth 92 or other means for maintaining registration. Blocks are provided with dielectric constants to achieve different frequency response relative to other pins. To achieve great EMI and cross talk isolation, the socket may be made of aluminum with hard anodize coating to insulate test pins (32) from the housing. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10794933B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10794933B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10794933B13</originalsourceid><addsrcrecordid>eNqNyjEKAjEQRuE0FqLeYTyA4BJBtl1R3Fqtl2Ey6wY0CckfvL4KHsDqFe-bm74P0HtmqCPxWaoHSQxgAUELiFPiz66FXh4TcXD0VEzRURy_siBXgY9haWYjP4qufl2Y9el4PZw3muKgJbFoUAy3S7Pdt7vW2q6x_5g3KjE1cQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit contact test apparatus with and method of construction</title><source>esp@cenet</source><creator>Erdman, Joel ; Sherry, Jeffrey</creator><creatorcontrib>Erdman, Joel ; Sherry, Jeffrey</creatorcontrib><description>A test socket for a device under test (DUT) is disclosed in several embodiments. One embodiment shows a test socket base (16) with apertures (30) for insertion of test pin insert blocks (28). The blocks are inserted top-in or bottom-in and are provided with registration bosses 80 and teeth 92 or other means for maintaining registration. Blocks are provided with dielectric constants to achieve different frequency response relative to other pins. To achieve great EMI and cross talk isolation, the socket may be made of aluminum with hard anodize coating to insulate test pins (32) from the housing.</description><language>eng</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201006&DB=EPODOC&CC=US&NR=10794933B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201006&DB=EPODOC&CC=US&NR=10794933B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Erdman, Joel</creatorcontrib><creatorcontrib>Sherry, Jeffrey</creatorcontrib><title>Integrated circuit contact test apparatus with and method of construction</title><description>A test socket for a device under test (DUT) is disclosed in several embodiments. One embodiment shows a test socket base (16) with apertures (30) for insertion of test pin insert blocks (28). The blocks are inserted top-in or bottom-in and are provided with registration bosses 80 and teeth 92 or other means for maintaining registration. Blocks are provided with dielectric constants to achieve different frequency response relative to other pins. To achieve great EMI and cross talk isolation, the socket may be made of aluminum with hard anodize coating to insulate test pins (32) from the housing.</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEKAjEQRuE0FqLeYTyA4BJBtl1R3Fqtl2Ey6wY0CckfvL4KHsDqFe-bm74P0HtmqCPxWaoHSQxgAUELiFPiz66FXh4TcXD0VEzRURy_siBXgY9haWYjP4qufl2Y9el4PZw3muKgJbFoUAy3S7Pdt7vW2q6x_5g3KjE1cQ</recordid><startdate>20201006</startdate><enddate>20201006</enddate><creator>Erdman, Joel</creator><creator>Sherry, Jeffrey</creator><scope>EVB</scope></search><sort><creationdate>20201006</creationdate><title>Integrated circuit contact test apparatus with and method of construction</title><author>Erdman, Joel ; Sherry, Jeffrey</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10794933B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>Erdman, Joel</creatorcontrib><creatorcontrib>Sherry, Jeffrey</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Erdman, Joel</au><au>Sherry, Jeffrey</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit contact test apparatus with and method of construction</title><date>2020-10-06</date><risdate>2020</risdate><abstract>A test socket for a device under test (DUT) is disclosed in several embodiments. One embodiment shows a test socket base (16) with apertures (30) for insertion of test pin insert blocks (28). The blocks are inserted top-in or bottom-in and are provided with registration bosses 80 and teeth 92 or other means for maintaining registration. Blocks are provided with dielectric constants to achieve different frequency response relative to other pins. To achieve great EMI and cross talk isolation, the socket may be made of aluminum with hard anodize coating to insulate test pins (32) from the housing.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US10794933B1 |
| source | esp@cenet |
| subjects | MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING |
| title | Integrated circuit contact test apparatus with and method of construction |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T23%3A50%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Erdman,%20Joel&rft.date=2020-10-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10794933B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |