Wafer level package structure and wafer level packaging method
Wafer level package structures and packaging methods are provided. An exemplary method includes providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated in the first front surface; forming a first o...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Luo, Hailong Drowley, Clifford Ian |
description | Wafer level package structures and packaging methods are provided. An exemplary method includes providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated in the first front surface; forming a first oxide layer on the first front surface of the device wafer; providing at least one second chip having a to-be-bonded surface; forming a second oxide layer on the to-be-bonded surface of each second chip; providing a carrier wafer; temporally bonding a surface of the second chip opposing the second oxide layer to the carrier wafer; forming an encapsulation layer on the carrier wafer between adjacent second chips of the at least one second; and bonding the device wafer and the second chip by bonding the first oxide layer with the second oxide layer by a low-temperature fusion bonding process. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10784229B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10784229B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10784229B23</originalsourceid><addsrcrecordid>eNrjZLALT0xLLVLISS1LzVEoSEzOTkxPVSguKSpNLiktSlVIzEtRKMdQkZmXrpCbWpKRn8LDwJqWmFOcyguluRkU3VxDnD10Uwvy41OLgcpT81JL4kODDQ3MLUyMjCydjIyJUQMAUiswqw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Wafer level package structure and wafer level packaging method</title><source>esp@cenet</source><creator>Luo, Hailong ; Drowley, Clifford Ian</creator><creatorcontrib>Luo, Hailong ; Drowley, Clifford Ian</creatorcontrib><description>Wafer level package structures and packaging methods are provided. An exemplary method includes providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated in the first front surface; forming a first oxide layer on the first front surface of the device wafer; providing at least one second chip having a to-be-bonded surface; forming a second oxide layer on the to-be-bonded surface of each second chip; providing a carrier wafer; temporally bonding a surface of the second chip opposing the second oxide layer to the carrier wafer; forming an encapsulation layer on the carrier wafer between adjacent second chips of the at least one second; and bonding the device wafer and the second chip by bonding the first oxide layer with the second oxide layer by a low-temperature fusion bonding process.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200922&DB=EPODOC&CC=US&NR=10784229B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200922&DB=EPODOC&CC=US&NR=10784229B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Luo, Hailong</creatorcontrib><creatorcontrib>Drowley, Clifford Ian</creatorcontrib><title>Wafer level package structure and wafer level packaging method</title><description>Wafer level package structures and packaging methods are provided. An exemplary method includes providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated in the first front surface; forming a first oxide layer on the first front surface of the device wafer; providing at least one second chip having a to-be-bonded surface; forming a second oxide layer on the to-be-bonded surface of each second chip; providing a carrier wafer; temporally bonding a surface of the second chip opposing the second oxide layer to the carrier wafer; forming an encapsulation layer on the carrier wafer between adjacent second chips of the at least one second; and bonding the device wafer and the second chip by bonding the first oxide layer with the second oxide layer by a low-temperature fusion bonding process.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLALT0xLLVLISS1LzVEoSEzOTkxPVSguKSpNLiktSlVIzEtRKMdQkZmXrpCbWpKRn8LDwJqWmFOcyguluRkU3VxDnD10Uwvy41OLgcpT81JL4kODDQ3MLUyMjCydjIyJUQMAUiswqw</recordid><startdate>20200922</startdate><enddate>20200922</enddate><creator>Luo, Hailong</creator><creator>Drowley, Clifford Ian</creator><scope>EVB</scope></search><sort><creationdate>20200922</creationdate><title>Wafer level package structure and wafer level packaging method</title><author>Luo, Hailong ; Drowley, Clifford Ian</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10784229B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Luo, Hailong</creatorcontrib><creatorcontrib>Drowley, Clifford Ian</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Luo, Hailong</au><au>Drowley, Clifford Ian</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Wafer level package structure and wafer level packaging method</title><date>2020-09-22</date><risdate>2020</risdate><abstract>Wafer level package structures and packaging methods are provided. An exemplary method includes providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated in the first front surface; forming a first oxide layer on the first front surface of the device wafer; providing at least one second chip having a to-be-bonded surface; forming a second oxide layer on the to-be-bonded surface of each second chip; providing a carrier wafer; temporally bonding a surface of the second chip opposing the second oxide layer to the carrier wafer; forming an encapsulation layer on the carrier wafer between adjacent second chips of the at least one second; and bonding the device wafer and the second chip by bonding the first oxide layer with the second oxide layer by a low-temperature fusion bonding process.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US10784229B2 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Wafer level package structure and wafer level packaging method |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T04%3A50%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Luo,%20Hailong&rft.date=2020-09-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10784229B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |