Built-in self-test (BIST) circuit, memory device including the same, and method of operating the BIST circuit

A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The...

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Bibliographische Detailangaben
Hauptverfasser: Park, Ki-hyun, Ok, Seung-ho, Shin, Sang-hoon, Zhang, Pyung-moon, Park, Yong-sik
Format: Patent
Sprache:eng
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