Automatic simulation failures analysis flow for functional verification

Disclosed is a system and method for automatically diagnosing an error by performing failure analysis of functional simulation pertaining to a Design Under Verification (DUV) or System Under Verification (SUV). A prediction unit generates a set of expected output packets upon processing a set of inp...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Krishnamoorthy, Sathish Kumar, Muthiah, Manickam
Format: Patent
Sprache:eng
Schlagworte:
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