Automatic simulation failures analysis flow for functional verification

Disclosed is a system and method for automatically diagnosing an error by performing failure analysis of functional simulation pertaining to a Design Under Verification (DUV) or System Under Verification (SUV). A prediction unit generates a set of expected output packets upon processing a set of inp...

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Hauptverfasser: Krishnamoorthy, Sathish Kumar, Muthiah, Manickam
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creator Krishnamoorthy, Sathish Kumar
Muthiah, Manickam
description Disclosed is a system and method for automatically diagnosing an error by performing failure analysis of functional simulation pertaining to a Design Under Verification (DUV) or System Under Verification (SUV). A prediction unit generates a set of expected output packets upon processing a set of input packets' copy. A comparison unit compares an actual output packet, from the set of actual output packets, with an expected output packet, from the set of expected output packets, corresponding to the actual output packet. When there is a mismatch, the actual output packet is compared with at least one subsequent expected output packet until the match is found. The diagnosing unit automatically diagnoses at least one of a packet drop error, an ordering error, an error in routing, by performing a systematic failure analysis and reports a diagnostic information and/or default diagnostic information associated with the error.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10769332B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10769332B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10769332B23</originalsourceid><addsrcrecordid>eNrjZHB3LC3Jz00syUxWKM7MLc0BsvLzFNISM3NKi1KLFRLzEnMqizOLFdJy8ssV0vKLFNJK85JBahJzFMpSizLTMpPBWngYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSXxosKGBuZmlsbGRk5ExMWoA6nM1IA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Automatic simulation failures analysis flow for functional verification</title><source>esp@cenet</source><creator>Krishnamoorthy, Sathish Kumar ; Muthiah, Manickam</creator><creatorcontrib>Krishnamoorthy, Sathish Kumar ; Muthiah, Manickam</creatorcontrib><description>Disclosed is a system and method for automatically diagnosing an error by performing failure analysis of functional simulation pertaining to a Design Under Verification (DUV) or System Under Verification (SUV). A prediction unit generates a set of expected output packets upon processing a set of input packets' copy. A comparison unit compares an actual output packet, from the set of actual output packets, with an expected output packet, from the set of expected output packets, corresponding to the actual output packet. When there is a mismatch, the actual output packet is compared with at least one subsequent expected output packet until the match is found. The diagnosing unit automatically diagnoses at least one of a packet drop error, an ordering error, an error in routing, by performing a systematic failure analysis and reports a diagnostic information and/or default diagnostic information associated with the error.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200908&amp;DB=EPODOC&amp;CC=US&amp;NR=10769332B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200908&amp;DB=EPODOC&amp;CC=US&amp;NR=10769332B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Krishnamoorthy, Sathish Kumar</creatorcontrib><creatorcontrib>Muthiah, Manickam</creatorcontrib><title>Automatic simulation failures analysis flow for functional verification</title><description>Disclosed is a system and method for automatically diagnosing an error by performing failure analysis of functional simulation pertaining to a Design Under Verification (DUV) or System Under Verification (SUV). A prediction unit generates a set of expected output packets upon processing a set of input packets' copy. A comparison unit compares an actual output packet, from the set of actual output packets, with an expected output packet, from the set of expected output packets, corresponding to the actual output packet. When there is a mismatch, the actual output packet is compared with at least one subsequent expected output packet until the match is found. The diagnosing unit automatically diagnoses at least one of a packet drop error, an ordering error, an error in routing, by performing a systematic failure analysis and reports a diagnostic information and/or default diagnostic information associated with the error.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHB3LC3Jz00syUxWKM7MLc0BsvLzFNISM3NKi1KLFRLzEnMqizOLFdJy8ssV0vKLFNJK85JBahJzFMpSizLTMpPBWngYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSXxosKGBuZmlsbGRk5ExMWoA6nM1IA</recordid><startdate>20200908</startdate><enddate>20200908</enddate><creator>Krishnamoorthy, Sathish Kumar</creator><creator>Muthiah, Manickam</creator><scope>EVB</scope></search><sort><creationdate>20200908</creationdate><title>Automatic simulation failures analysis flow for functional verification</title><author>Krishnamoorthy, Sathish Kumar ; Muthiah, Manickam</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10769332B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Krishnamoorthy, Sathish Kumar</creatorcontrib><creatorcontrib>Muthiah, Manickam</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Krishnamoorthy, Sathish Kumar</au><au>Muthiah, Manickam</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Automatic simulation failures analysis flow for functional verification</title><date>2020-09-08</date><risdate>2020</risdate><abstract>Disclosed is a system and method for automatically diagnosing an error by performing failure analysis of functional simulation pertaining to a Design Under Verification (DUV) or System Under Verification (SUV). A prediction unit generates a set of expected output packets upon processing a set of input packets' copy. A comparison unit compares an actual output packet, from the set of actual output packets, with an expected output packet, from the set of expected output packets, corresponding to the actual output packet. When there is a mismatch, the actual output packet is compared with at least one subsequent expected output packet until the match is found. The diagnosing unit automatically diagnoses at least one of a packet drop error, an ordering error, an error in routing, by performing a systematic failure analysis and reports a diagnostic information and/or default diagnostic information associated with the error.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Automatic simulation failures analysis flow for functional verification
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-17T01%3A00%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Krishnamoorthy,%20Sathish%20Kumar&rft.date=2020-09-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10769332B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true