Hardware micro-services platform

A device comprising: at least one partially reconfigurable FPGA; a Network-on-Chip (NoC) comprised in the FPGA; and at least one area on the at least one FPGA operable to house a hardware micro-service (HMS); wherein an HMS image may be loaded onto the area of the at least one FPGA via partial recon...

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Hauptverfasser: Sorani, Yzhak, Stein, Yaakov
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creator Sorani, Yzhak
Stein, Yaakov
description A device comprising: at least one partially reconfigurable FPGA; a Network-on-Chip (NoC) comprised in the FPGA; and at least one area on the at least one FPGA operable to house a hardware micro-service (HMS); wherein an HMS image may be loaded onto the area of the at least one FPGA via partial reconfiguration to form a new HMS, and the NoC is operable to forward information to and from the new HMS without the NoC being reloaded.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10754666B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10754666B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10754666B13</originalsourceid><addsrcrecordid>eNrjZFDwSCxKKU8sSlXIzUwuytctTi0qy0xOLVYoyEksScsvyuVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYYG5qYmZmZmTobGxKgBAHPIJb0</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Hardware micro-services platform</title><source>esp@cenet</source><creator>Sorani, Yzhak ; Stein, Yaakov</creator><creatorcontrib>Sorani, Yzhak ; Stein, Yaakov</creatorcontrib><description>A device comprising: at least one partially reconfigurable FPGA; a Network-on-Chip (NoC) comprised in the FPGA; and at least one area on the at least one FPGA operable to house a hardware micro-service (HMS); wherein an HMS image may be loaded onto the area of the at least one FPGA via partial reconfiguration to form a new HMS, and the NoC is operable to forward information to and from the new HMS without the NoC being reloaded.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200825&amp;DB=EPODOC&amp;CC=US&amp;NR=10754666B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200825&amp;DB=EPODOC&amp;CC=US&amp;NR=10754666B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Sorani, Yzhak</creatorcontrib><creatorcontrib>Stein, Yaakov</creatorcontrib><title>Hardware micro-services platform</title><description>A device comprising: at least one partially reconfigurable FPGA; a Network-on-Chip (NoC) comprised in the FPGA; and at least one area on the at least one FPGA operable to house a hardware micro-service (HMS); wherein an HMS image may be loaded onto the area of the at least one FPGA via partial reconfiguration to form a new HMS, and the NoC is operable to forward information to and from the new HMS without the NoC being reloaded.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFDwSCxKKU8sSlXIzUwuytctTi0qy0xOLVYoyEksScsvyuVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYYG5qYmZmZmTobGxKgBAHPIJb0</recordid><startdate>20200825</startdate><enddate>20200825</enddate><creator>Sorani, Yzhak</creator><creator>Stein, Yaakov</creator><scope>EVB</scope></search><sort><creationdate>20200825</creationdate><title>Hardware micro-services platform</title><author>Sorani, Yzhak ; Stein, Yaakov</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10754666B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Sorani, Yzhak</creatorcontrib><creatorcontrib>Stein, Yaakov</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sorani, Yzhak</au><au>Stein, Yaakov</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Hardware micro-services platform</title><date>2020-08-25</date><risdate>2020</risdate><abstract>A device comprising: at least one partially reconfigurable FPGA; a Network-on-Chip (NoC) comprised in the FPGA; and at least one area on the at least one FPGA operable to house a hardware micro-service (HMS); wherein an HMS image may be loaded onto the area of the at least one FPGA via partial reconfiguration to form a new HMS, and the NoC is operable to forward information to and from the new HMS without the NoC being reloaded.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Hardware micro-services platform
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T13%3A42%3A12IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Sorani,%20Yzhak&rft.date=2020-08-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10754666B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true