Circuit structure for adjusting PTAT current to compensate for process variations in device transistor
The disclosure provides a circuit structure including a current source including at least one FDSOI transistor having a back-gate terminal, wherein the current source generates a current proportionate to an absolute temperature of the circuit structure; a first current mirror electrically coupled to...
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| creator | Fang, Sher Jiun Lee, See Taur |
| description | The disclosure provides a circuit structure including a current source including at least one FDSOI transistor having a back-gate terminal, wherein the current source generates a current proportionate to an absolute temperature of the circuit structure; a first current mirror electrically coupled to the current source and a gate terminal of a device transistor, wherein the first current mirror applies a gate bias to the device transistor based on a magnitude of the current, and wherein a source or drain terminal of the device transistor includes an output current of the circuit structure; and an adjustable voltage source coupled to the back-gate terminal of the at least one FDSOI transistor of the current source, wherein the adjustable voltage source applies a selected back-gate bias voltage to the back-gate terminal of the at least one FDSOI transistor to adjust the current to compensate for process variations of the device transistor. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10747254B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10747254B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10747254B13</originalsourceid><addsrcrecordid>eNqNyjEKwlAMANAuDqLeIR5AsFrprEVxFKxzCb9piWj-J8nv-R30AE5vefNiaFhDZgdzzcGzEgxRAftnNmcZ4dYeWwhZlcTBI4T4TiSG_o1JYyAzmFAZnaMYsEBPEwcCVxRj86jLYjbgy2j1c1GsL-e2uW4oxY4sYSAh7x73cltX9e5Qncr9P-cDwntAYw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Circuit structure for adjusting PTAT current to compensate for process variations in device transistor</title><source>esp@cenet</source><creator>Fang, Sher Jiun ; Lee, See Taur</creator><creatorcontrib>Fang, Sher Jiun ; Lee, See Taur</creatorcontrib><description>The disclosure provides a circuit structure including a current source including at least one FDSOI transistor having a back-gate terminal, wherein the current source generates a current proportionate to an absolute temperature of the circuit structure; a first current mirror electrically coupled to the current source and a gate terminal of a device transistor, wherein the first current mirror applies a gate bias to the device transistor based on a magnitude of the current, and wherein a source or drain terminal of the device transistor includes an output current of the circuit structure; and an adjustable voltage source coupled to the back-gate terminal of the at least one FDSOI transistor of the current source, wherein the adjustable voltage source applies a selected back-gate bias voltage to the back-gate terminal of the at least one FDSOI transistor to adjust the current to compensate for process variations of the device transistor.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CONTROLLING ; ELECTRICITY ; PHYSICS ; PULSE TECHNIQUE ; REGULATING ; SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200818&DB=EPODOC&CC=US&NR=10747254B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200818&DB=EPODOC&CC=US&NR=10747254B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Fang, Sher Jiun</creatorcontrib><creatorcontrib>Lee, See Taur</creatorcontrib><title>Circuit structure for adjusting PTAT current to compensate for process variations in device transistor</title><description>The disclosure provides a circuit structure including a current source including at least one FDSOI transistor having a back-gate terminal, wherein the current source generates a current proportionate to an absolute temperature of the circuit structure; a first current mirror electrically coupled to the current source and a gate terminal of a device transistor, wherein the first current mirror applies a gate bias to the device transistor based on a magnitude of the current, and wherein a source or drain terminal of the device transistor includes an output current of the circuit structure; and an adjustable voltage source coupled to the back-gate terminal of the at least one FDSOI transistor of the current source, wherein the adjustable voltage source applies a selected back-gate bias voltage to the back-gate terminal of the at least one FDSOI transistor to adjust the current to compensate for process variations of the device transistor.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CONTROLLING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>REGULATING</subject><subject>SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEKwlAMANAuDqLeIR5AsFrprEVxFKxzCb9piWj-J8nv-R30AE5vefNiaFhDZgdzzcGzEgxRAftnNmcZ4dYeWwhZlcTBI4T4TiSG_o1JYyAzmFAZnaMYsEBPEwcCVxRj86jLYjbgy2j1c1GsL-e2uW4oxY4sYSAh7x73cltX9e5Qncr9P-cDwntAYw</recordid><startdate>20200818</startdate><enddate>20200818</enddate><creator>Fang, Sher Jiun</creator><creator>Lee, See Taur</creator><scope>EVB</scope></search><sort><creationdate>20200818</creationdate><title>Circuit structure for adjusting PTAT current to compensate for process variations in device transistor</title><author>Fang, Sher Jiun ; Lee, See Taur</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10747254B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CONTROLLING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>REGULATING</topic><topic>SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</topic><toplevel>online_resources</toplevel><creatorcontrib>Fang, Sher Jiun</creatorcontrib><creatorcontrib>Lee, See Taur</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fang, Sher Jiun</au><au>Lee, See Taur</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Circuit structure for adjusting PTAT current to compensate for process variations in device transistor</title><date>2020-08-18</date><risdate>2020</risdate><abstract>The disclosure provides a circuit structure including a current source including at least one FDSOI transistor having a back-gate terminal, wherein the current source generates a current proportionate to an absolute temperature of the circuit structure; a first current mirror electrically coupled to the current source and a gate terminal of a device transistor, wherein the first current mirror applies a gate bias to the device transistor based on a magnitude of the current, and wherein a source or drain terminal of the device transistor includes an output current of the circuit structure; and an adjustable voltage source coupled to the back-gate terminal of the at least one FDSOI transistor of the current source, wherein the adjustable voltage source applies a selected back-gate bias voltage to the back-gate terminal of the at least one FDSOI transistor to adjust the current to compensate for process variations of the device transistor.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY CONTROLLING ELECTRICITY PHYSICS PULSE TECHNIQUE REGULATING SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES |
| title | Circuit structure for adjusting PTAT current to compensate for process variations in device transistor |
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