Rectangular via for ensuring via yield in the absence of via redundancy

A rectangular via extending between interconnects in different metallization levels can have a planform with a width equal to the width of the interconnects and a length equal to twice the width and can be aligned along a long dimension with a length of the upper interconnect. In an integrated circu...

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1. Verfasser: Blatchford, James Walter
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description A rectangular via extending between interconnects in different metallization levels can have a planform with a width equal to the width of the interconnects and a length equal to twice the width and can be aligned along a long dimension with a length of the upper interconnect. In an integrated circuit layout, the planform can be centered over the width of the lower interconnect, allowing for misalignment during fabrication while maintaining a robust electrical connection. The bottom of the via may be aligned with an upper surface of the lower interconnect or may include portions below the lower interconnect's upper surface. Fewer adjacent routing tracks are blocked by use of the rectangular via than would be blocked using redundant square vias, while ensuring reliability of the electrical connection despite potential misalignment during fabrication.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10741489B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10741489B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10741489B23</originalsourceid><addsrcrecordid>eNrjZHAPSk0uScxLL81JLFIoy0xUSMsvUkjNKy4tysxLBwtUZqbmpChk5imUZKQqJCYVp-Ylpyrkp4HlilJTSvNSEvOSK3kYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSXxosKGBuYmhiYWlk5ExMWoAPGIzsg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Rectangular via for ensuring via yield in the absence of via redundancy</title><source>esp@cenet</source><creator>Blatchford, James Walter</creator><creatorcontrib>Blatchford, James Walter</creatorcontrib><description>A rectangular via extending between interconnects in different metallization levels can have a planform with a width equal to the width of the interconnects and a length equal to twice the width and can be aligned along a long dimension with a length of the upper interconnect. In an integrated circuit layout, the planform can be centered over the width of the lower interconnect, allowing for misalignment during fabrication while maintaining a robust electrical connection. The bottom of the via may be aligned with an upper surface of the lower interconnect or may include portions below the lower interconnect's upper surface. Fewer adjacent routing tracks are blocked by use of the rectangular via than would be blocked using redundant square vias, while ensuring reliability of the electrical connection despite potential misalignment during fabrication.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200811&amp;DB=EPODOC&amp;CC=US&amp;NR=10741489B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200811&amp;DB=EPODOC&amp;CC=US&amp;NR=10741489B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Blatchford, James Walter</creatorcontrib><title>Rectangular via for ensuring via yield in the absence of via redundancy</title><description>A rectangular via extending between interconnects in different metallization levels can have a planform with a width equal to the width of the interconnects and a length equal to twice the width and can be aligned along a long dimension with a length of the upper interconnect. In an integrated circuit layout, the planform can be centered over the width of the lower interconnect, allowing for misalignment during fabrication while maintaining a robust electrical connection. The bottom of the via may be aligned with an upper surface of the lower interconnect or may include portions below the lower interconnect's upper surface. Fewer adjacent routing tracks are blocked by use of the rectangular via than would be blocked using redundant square vias, while ensuring reliability of the electrical connection despite potential misalignment during fabrication.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAPSk0uScxLL81JLFIoy0xUSMsvUkjNKy4tysxLBwtUZqbmpChk5imUZKQqJCYVp-Ylpyrkp4HlilJTSvNSEvOSK3kYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSXxosKGBuYmhiYWlk5ExMWoAPGIzsg</recordid><startdate>20200811</startdate><enddate>20200811</enddate><creator>Blatchford, James Walter</creator><scope>EVB</scope></search><sort><creationdate>20200811</creationdate><title>Rectangular via for ensuring via yield in the absence of via redundancy</title><author>Blatchford, James Walter</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10741489B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Blatchford, James Walter</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Blatchford, James Walter</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Rectangular via for ensuring via yield in the absence of via redundancy</title><date>2020-08-11</date><risdate>2020</risdate><abstract>A rectangular via extending between interconnects in different metallization levels can have a planform with a width equal to the width of the interconnects and a length equal to twice the width and can be aligned along a long dimension with a length of the upper interconnect. In an integrated circuit layout, the planform can be centered over the width of the lower interconnect, allowing for misalignment during fabrication while maintaining a robust electrical connection. The bottom of the via may be aligned with an upper surface of the lower interconnect or may include portions below the lower interconnect's upper surface. Fewer adjacent routing tracks are blocked by use of the rectangular via than would be blocked using redundant square vias, while ensuring reliability of the electrical connection despite potential misalignment during fabrication.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Rectangular via for ensuring via yield in the absence of via redundancy
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T15%3A57%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Blatchford,%20James%20Walter&rft.date=2020-08-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10741489B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true