Interface circuit

Interface circuit

A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or leve...

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Hauptverfasser: Pihet, Eric, Hinderer, Thorsten, Mangst, Maximilian
Format: Patent
Sprache:eng
Schlagworte:
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator Pihet, Eric
Hinderer, Thorsten
Mangst, Maximilian
description A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or levels of said further data stream. A symbol sequence is constructed from the first symbols and second symbols, wherein said symbol sequence is constructed in such a manner that the first symbols are always delayed by the same value relative to the associated edges of the first data stream. The method also comprises transmitting the symbol sequence via a galvanically isolating component, and decoding the symbol sequence transmitted via the galvanically isolating component in order to reconstruct the first data stream and the further data stream.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10728064B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10728064B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10728064B23</originalsourceid><addsrcrecordid>eNrjZBD0zCtJLUpLTE5VSM4sSi7NLOFhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBUCleakl8aHBhgbmRhYGZiZORsbEqAEA1w8fyA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Interface circuit</title><source>esp@cenet</source><creator>Pihet, Eric ; Hinderer, Thorsten ; Mangst, Maximilian</creator><creatorcontrib>Pihet, Eric ; Hinderer, Thorsten ; Mangst, Maximilian</creatorcontrib><description>A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or levels of said further data stream. A symbol sequence is constructed from the first symbols and second symbols, wherein said symbol sequence is constructed in such a manner that the first symbols are always delayed by the same value relative to the associated edges of the first data stream. The method also comprises transmitting the symbol sequence via a galvanically isolating component, and decoding the symbol sequence transmitted via the galvanically isolating component in order to reconstruct the first data stream and the further data stream.</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200728&amp;DB=EPODOC&amp;CC=US&amp;NR=10728064B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200728&amp;DB=EPODOC&amp;CC=US&amp;NR=10728064B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Pihet, Eric</creatorcontrib><creatorcontrib>Hinderer, Thorsten</creatorcontrib><creatorcontrib>Mangst, Maximilian</creatorcontrib><title>Interface circuit</title><description>A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or levels of said further data stream. A symbol sequence is constructed from the first symbols and second symbols, wherein said symbol sequence is constructed in such a manner that the first symbols are always delayed by the same value relative to the associated edges of the first data stream. The method also comprises transmitting the symbol sequence via a galvanically isolating component, and decoding the symbol sequence transmitted via the galvanically isolating component in order to reconstruct the first data stream and the further data stream.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBD0zCtJLUpLTE5VSM4sSi7NLOFhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBUCleakl8aHBhgbmRhYGZiZORsbEqAEA1w8fyA</recordid><startdate>20200728</startdate><enddate>20200728</enddate><creator>Pihet, Eric</creator><creator>Hinderer, Thorsten</creator><creator>Mangst, Maximilian</creator><scope>EVB</scope></search><sort><creationdate>20200728</creationdate><title>Interface circuit</title><author>Pihet, Eric ; Hinderer, Thorsten ; Mangst, Maximilian</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10728064B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>Pihet, Eric</creatorcontrib><creatorcontrib>Hinderer, Thorsten</creatorcontrib><creatorcontrib>Mangst, Maximilian</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Pihet, Eric</au><au>Hinderer, Thorsten</au><au>Mangst, Maximilian</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Interface circuit</title><date>2020-07-28</date><risdate>2020</risdate><abstract>A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or levels of said further data stream. A symbol sequence is constructed from the first symbols and second symbols, wherein said symbol sequence is constructed in such a manner that the first symbols are always delayed by the same value relative to the associated edges of the first data stream. The method also comprises transmitting the symbol sequence via a galvanically isolating component, and decoding the symbol sequence transmitted via the galvanically isolating component in order to reconstruct the first data stream and the further data stream.</abstract><oa>free_for_read</oa></addata></record>
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subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title Interface circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T07%3A59%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Pihet,%20Eric&rft.date=2020-07-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10728064B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true