Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at...
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| creator | Oh, Kyung Seob Kim, Jong Rip Lee, Doo Hwan Kim, Hyoung Joon Kim, Jin Yul |
| description | A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and the passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member. |
| format | Patent |
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The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and the passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200714&DB=EPODOC&CC=US&NR=10714437B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200714&DB=EPODOC&CC=US&NR=10714437B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Oh, Kyung Seob</creatorcontrib><creatorcontrib>Kim, Jong Rip</creatorcontrib><creatorcontrib>Lee, Doo Hwan</creatorcontrib><creatorcontrib>Kim, Hyoung Joon</creatorcontrib><creatorcontrib>Kim, Jin Yul</creatorcontrib><title>Fan-out semiconductor package</title><description>A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and the passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJB1S8zTzS8tUShOzc1Mzs9LKU0uyS9SKEhMzk5MT-VhYE1LzClO5YXS3AyKbq4hzh66qQX58anFQFWpeakl8aHBhgbmhiYmxuZORsbEqAEA02AkUw</recordid><startdate>20200714</startdate><enddate>20200714</enddate><creator>Oh, Kyung Seob</creator><creator>Kim, Jong Rip</creator><creator>Lee, Doo Hwan</creator><creator>Kim, Hyoung Joon</creator><creator>Kim, Jin Yul</creator><scope>EVB</scope></search><sort><creationdate>20200714</creationdate><title>Fan-out semiconductor package</title><author>Oh, Kyung Seob ; Kim, Jong Rip ; Lee, Doo Hwan ; Kim, Hyoung Joon ; Kim, Jin Yul</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10714437B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Oh, Kyung Seob</creatorcontrib><creatorcontrib>Kim, Jong Rip</creatorcontrib><creatorcontrib>Lee, Doo Hwan</creatorcontrib><creatorcontrib>Kim, Hyoung Joon</creatorcontrib><creatorcontrib>Kim, Jin Yul</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Oh, Kyung Seob</au><au>Kim, Jong Rip</au><au>Lee, Doo Hwan</au><au>Kim, Hyoung Joon</au><au>Kim, Jin Yul</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Fan-out semiconductor package</title><date>2020-07-14</date><risdate>2020</risdate><abstract>A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and the passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
| title | Fan-out semiconductor package |
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