Data processing system with a scalable architecture over ethernet
According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root inclu...
Gespeichert in:
Hauptverfasser: | , , , , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Barnett, Blair Wilde, Todd Rowett, Kevin Wilford, Bruce Durai, Vishwas Gaasbeck, Richard Van Carlson, Rick Himelstein, Mark Venkataraghavan, Vikram |
description | According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10713334B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10713334B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10713334B13</originalsourceid><addsrcrecordid>eNqNyjsKQjEQBdA0FqLuYVyAYIhg7Rd7tX6Mw9UE4kvIjIq718IFWJ3mDN1qy8ZUWxGopv5G-lbDnV7JIjGpcOZLBnGTmAxijwYqTzSCRbQeNnaDK2fF5OfITfe70-YwQy0dtLLgu7rz0c-XPoSwWPvwz_kAJdQyFA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Data processing system with a scalable architecture over ethernet</title><source>esp@cenet</source><creator>Barnett, Blair ; Wilde, Todd ; Rowett, Kevin ; Wilford, Bruce ; Durai, Vishwas ; Gaasbeck, Richard Van ; Carlson, Rick ; Himelstein, Mark ; Venkataraghavan, Vikram</creator><creatorcontrib>Barnett, Blair ; Wilde, Todd ; Rowett, Kevin ; Wilford, Bruce ; Durai, Vishwas ; Gaasbeck, Richard Van ; Carlson, Rick ; Himelstein, Mark ; Venkataraghavan, Vikram</creatorcontrib><description>According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; CONTROL OR REGULATING SYSTEMS IN GENERAL ; CONTROLLING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS ; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS ; PHYSICS ; REGULATING</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200714&DB=EPODOC&CC=US&NR=10713334B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200714&DB=EPODOC&CC=US&NR=10713334B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Barnett, Blair</creatorcontrib><creatorcontrib>Wilde, Todd</creatorcontrib><creatorcontrib>Rowett, Kevin</creatorcontrib><creatorcontrib>Wilford, Bruce</creatorcontrib><creatorcontrib>Durai, Vishwas</creatorcontrib><creatorcontrib>Gaasbeck, Richard Van</creatorcontrib><creatorcontrib>Carlson, Rick</creatorcontrib><creatorcontrib>Himelstein, Mark</creatorcontrib><creatorcontrib>Venkataraghavan, Vikram</creatorcontrib><title>Data processing system with a scalable architecture over ethernet</title><description>According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>CONTROL OR REGULATING SYSTEMS IN GENERAL</subject><subject>CONTROLLING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</subject><subject>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</subject><subject>PHYSICS</subject><subject>REGULATING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjsKQjEQBdA0FqLuYVyAYIhg7Rd7tX6Mw9UE4kvIjIq718IFWJ3mDN1qy8ZUWxGopv5G-lbDnV7JIjGpcOZLBnGTmAxijwYqTzSCRbQeNnaDK2fF5OfITfe70-YwQy0dtLLgu7rz0c-XPoSwWPvwz_kAJdQyFA</recordid><startdate>20200714</startdate><enddate>20200714</enddate><creator>Barnett, Blair</creator><creator>Wilde, Todd</creator><creator>Rowett, Kevin</creator><creator>Wilford, Bruce</creator><creator>Durai, Vishwas</creator><creator>Gaasbeck, Richard Van</creator><creator>Carlson, Rick</creator><creator>Himelstein, Mark</creator><creator>Venkataraghavan, Vikram</creator><scope>EVB</scope></search><sort><creationdate>20200714</creationdate><title>Data processing system with a scalable architecture over ethernet</title><author>Barnett, Blair ; Wilde, Todd ; Rowett, Kevin ; Wilford, Bruce ; Durai, Vishwas ; Gaasbeck, Richard Van ; Carlson, Rick ; Himelstein, Mark ; Venkataraghavan, Vikram</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10713334B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>CONTROL OR REGULATING SYSTEMS IN GENERAL</topic><topic>CONTROLLING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</topic><topic>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</topic><topic>PHYSICS</topic><topic>REGULATING</topic><toplevel>online_resources</toplevel><creatorcontrib>Barnett, Blair</creatorcontrib><creatorcontrib>Wilde, Todd</creatorcontrib><creatorcontrib>Rowett, Kevin</creatorcontrib><creatorcontrib>Wilford, Bruce</creatorcontrib><creatorcontrib>Durai, Vishwas</creatorcontrib><creatorcontrib>Gaasbeck, Richard Van</creatorcontrib><creatorcontrib>Carlson, Rick</creatorcontrib><creatorcontrib>Himelstein, Mark</creatorcontrib><creatorcontrib>Venkataraghavan, Vikram</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Barnett, Blair</au><au>Wilde, Todd</au><au>Rowett, Kevin</au><au>Wilford, Bruce</au><au>Durai, Vishwas</au><au>Gaasbeck, Richard Van</au><au>Carlson, Rick</au><au>Himelstein, Mark</au><au>Venkataraghavan, Vikram</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Data processing system with a scalable architecture over ethernet</title><date>2020-07-14</date><risdate>2020</risdate><abstract>According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US10713334B1 |
source | esp@cenet |
subjects | CALCULATING COMPUTING CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING COUNTING ELECTRIC DIGITAL DATA PROCESSING FUNCTIONAL ELEMENTS OF SUCH SYSTEMS MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS REGULATING |
title | Data processing system with a scalable architecture over ethernet |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T19%3A45%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Barnett,%20Blair&rft.date=2020-07-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10713334B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |