Protection of high-K dielectric during reliability anneal on nanosheet structures

A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrate forming an interfacial layer over the nanosheets depositing a high-k dielectric layer conf...

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Hauptverfasser: Narayanan, Vijay, Loubet, Nicolas J, Sankarapandian, Muthumanickam, Mehta, Sanjay C
Format: Patent
Sprache:eng
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Zusammenfassung:A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrate forming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystalize the high-k dielectric layer.