Extended line width memory-side cache systems and methods

The present disclosure techniques for implementing an apparatus, which includes processing circuitry that performs an operation based a target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than t...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Korzh, Anton, Pawlowski, Stephen S, Murphy, Richard C
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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