Digital delay locked loop
The invention concerns a digital delay locked loop comprising: first and second digitally controllable delay lines (202B, 204B) coupled in series with each other, each comprising a lead portion (214, 218) and a lag portion (216, 220), the first digitally controllable delay line receiving a reference...
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| creator | Zarudniev, Mykhailo Pelissier, Michaël Sudalaiyandi, Shanthi Masson, Gilles |
| description | The invention concerns a digital delay locked loop comprising: first and second digitally controllable delay lines (202B, 204B) coupled in series with each other, each comprising a lead portion (214, 218) and a lag portion (216, 220), the first digitally controllable delay line receiving a reference timing signal (TREF) and the second digitally controllable delay line outputting a delayed timing signal (TREF); and a time to digital converter (212) configured to evaluate a phase difference between the reference signal (TREF) and the delayed timing signal (TREF′) and to generate a first control signal (DLEAD_[0:n]) for controlling said lead portions (214, 218) or a second control signal (DLAG[0:n]) for controlling said lag portions (216, 220) based on the sign and magnitude of the phase difference. |
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and a time to digital converter (212) configured to evaluate a phase difference between the reference signal (TREF) and the delayed timing signal (TREF′) and to generate a first control signal (DLEAD_[0:n]) for controlling said lead portions (214, 218) or a second control signal (DLAG[0:n]) for controlling said lag portions (216, 220) based on the sign and magnitude of the phase difference.</description><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200526&DB=EPODOC&CC=US&NR=10666270B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200526&DB=EPODOC&CC=US&NR=10666270B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Zarudniev, Mykhailo</creatorcontrib><creatorcontrib>Pelissier, Michaël</creatorcontrib><creatorcontrib>Sudalaiyandi, Shanthi</creatorcontrib><creatorcontrib>Masson, Gilles</creatorcontrib><title>Digital delay locked loop</title><description>The invention concerns a digital delay locked loop comprising: first and second digitally controllable delay lines (202B, 204B) coupled in series with each other, each comprising a lead portion (214, 218) and a lag portion (216, 220), the first digitally controllable delay line receiving a reference timing signal (TREF) and the second digitally controllable delay line outputting a delayed timing signal (TREF); and a time to digital converter (212) configured to evaluate a phase difference between the reference signal (TREF) and the delayed timing signal (TREF′) and to generate a first control signal (DLEAD_[0:n]) for controlling said lead portions (214, 218) or a second control signal (DLAG[0:n]) for controlling said lag portions (216, 220) based on the sign and magnitude of the phase difference.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJB0yUzPLEnMUUhJzUmsVMjJT85OTQFS-QU8DKxpiTnFqbxQmptB0c01xNlDN7UgPz61uCAxOTUvtSQ-NNjQwMzMzMjcwMnImBg1AAdFIoU</recordid><startdate>20200526</startdate><enddate>20200526</enddate><creator>Zarudniev, Mykhailo</creator><creator>Pelissier, Michaël</creator><creator>Sudalaiyandi, Shanthi</creator><creator>Masson, Gilles</creator><scope>EVB</scope></search><sort><creationdate>20200526</creationdate><title>Digital delay locked loop</title><author>Zarudniev, Mykhailo ; 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and a time to digital converter (212) configured to evaluate a phase difference between the reference signal (TREF) and the delayed timing signal (TREF′) and to generate a first control signal (DLEAD_[0:n]) for controlling said lead portions (214, 218) or a second control signal (DLAG[0:n]) for controlling said lag portions (216, 220) based on the sign and magnitude of the phase difference.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
| title | Digital delay locked loop |
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