Cell layout and structure
A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structure...
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| creator | Yeh, Yu-Cheng Hsieh, Tung-Heng Tsai, Tsung-Chieh Lee, Liang-Yao Wang, Sheng-Hsiung Ting, Jyh-Kang Wu, Juing-Yi Zhuang, Hui-Zhong |
| description | A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed. |
| format | Patent |
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In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200526&DB=EPODOC&CC=US&NR=10664639B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200526&DB=EPODOC&CC=US&NR=10664639B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Yeh, Yu-Cheng</creatorcontrib><creatorcontrib>Hsieh, Tung-Heng</creatorcontrib><creatorcontrib>Tsai, Tsung-Chieh</creatorcontrib><creatorcontrib>Lee, Liang-Yao</creatorcontrib><creatorcontrib>Wang, Sheng-Hsiung</creatorcontrib><creatorcontrib>Ting, Jyh-Kang</creatorcontrib><creatorcontrib>Wu, Juing-Yi</creatorcontrib><creatorcontrib>Zhuang, Hui-Zhong</creatorcontrib><title>Cell layout and structure</title><description>A post placement abutment treatment for cell row design is provided. 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By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJB0Ts3JUchJrMwvLVFIzEtRKC4pKk0uKS1K5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgZmZiZmxpZORsbEqAEAIe4i3A</recordid><startdate>20200526</startdate><enddate>20200526</enddate><creator>Yeh, Yu-Cheng</creator><creator>Hsieh, Tung-Heng</creator><creator>Tsai, Tsung-Chieh</creator><creator>Lee, Liang-Yao</creator><creator>Wang, Sheng-Hsiung</creator><creator>Ting, Jyh-Kang</creator><creator>Wu, Juing-Yi</creator><creator>Zhuang, Hui-Zhong</creator><scope>EVB</scope></search><sort><creationdate>20200526</creationdate><title>Cell layout and structure</title><author>Yeh, Yu-Cheng ; Hsieh, Tung-Heng ; Tsai, Tsung-Chieh ; Lee, Liang-Yao ; Wang, Sheng-Hsiung ; Ting, Jyh-Kang ; Wu, Juing-Yi ; Zhuang, Hui-Zhong</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10664639B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Yeh, Yu-Cheng</creatorcontrib><creatorcontrib>Hsieh, Tung-Heng</creatorcontrib><creatorcontrib>Tsai, Tsung-Chieh</creatorcontrib><creatorcontrib>Lee, Liang-Yao</creatorcontrib><creatorcontrib>Wang, Sheng-Hsiung</creatorcontrib><creatorcontrib>Ting, Jyh-Kang</creatorcontrib><creatorcontrib>Wu, Juing-Yi</creatorcontrib><creatorcontrib>Zhuang, Hui-Zhong</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yeh, Yu-Cheng</au><au>Hsieh, Tung-Heng</au><au>Tsai, Tsung-Chieh</au><au>Lee, Liang-Yao</au><au>Wang, Sheng-Hsiung</au><au>Ting, Jyh-Kang</au><au>Wu, Juing-Yi</au><au>Zhuang, Hui-Zhong</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Cell layout and structure</title><date>2020-05-26</date><risdate>2020</risdate><abstract>A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
| title | Cell layout and structure |
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