Selective recessing to form a fully aligned via
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric l...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Standaert, Theodorus E Lee, Joe Huang, Elbert E Briggs, Benjamin D Dechene, Jessica |
description | A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10636706B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10636706B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10636706B23</originalsourceid><addsrcrecordid>eNrjZNAPTs1JTS7JLEtVKEpNTi0uzsxLVyjJV0jLL8pVSFRIK83JqVRIzMlMz0tNUSjLTORhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYYGZsZm5gZmTkbGxKgBABQZKsM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Selective recessing to form a fully aligned via</title><source>esp@cenet</source><creator>Standaert, Theodorus E ; Lee, Joe ; Huang, Elbert E ; Briggs, Benjamin D ; Dechene, Jessica</creator><creatorcontrib>Standaert, Theodorus E ; Lee, Joe ; Huang, Elbert E ; Briggs, Benjamin D ; Dechene, Jessica</creatorcontrib><description>A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200428&DB=EPODOC&CC=US&NR=10636706B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200428&DB=EPODOC&CC=US&NR=10636706B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Standaert, Theodorus E</creatorcontrib><creatorcontrib>Lee, Joe</creatorcontrib><creatorcontrib>Huang, Elbert E</creatorcontrib><creatorcontrib>Briggs, Benjamin D</creatorcontrib><creatorcontrib>Dechene, Jessica</creatorcontrib><title>Selective recessing to form a fully aligned via</title><description>A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAPTs1JTS7JLEtVKEpNTi0uzsxLVyjJV0jLL8pVSFRIK83JqVRIzMlMz0tNUSjLTORhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYYGZsZm5gZmTkbGxKgBABQZKsM</recordid><startdate>20200428</startdate><enddate>20200428</enddate><creator>Standaert, Theodorus E</creator><creator>Lee, Joe</creator><creator>Huang, Elbert E</creator><creator>Briggs, Benjamin D</creator><creator>Dechene, Jessica</creator><scope>EVB</scope></search><sort><creationdate>20200428</creationdate><title>Selective recessing to form a fully aligned via</title><author>Standaert, Theodorus E ; Lee, Joe ; Huang, Elbert E ; Briggs, Benjamin D ; Dechene, Jessica</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10636706B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Standaert, Theodorus E</creatorcontrib><creatorcontrib>Lee, Joe</creatorcontrib><creatorcontrib>Huang, Elbert E</creatorcontrib><creatorcontrib>Briggs, Benjamin D</creatorcontrib><creatorcontrib>Dechene, Jessica</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Standaert, Theodorus E</au><au>Lee, Joe</au><au>Huang, Elbert E</au><au>Briggs, Benjamin D</au><au>Dechene, Jessica</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Selective recessing to form a fully aligned via</title><date>2020-04-28</date><risdate>2020</risdate><abstract>A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US10636706B2 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Selective recessing to form a fully aligned via |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-30T15%3A24%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Standaert,%20Theodorus%20E&rft.date=2020-04-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10636706B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |