Resistance memory cell

Resistance memory cell

A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply...

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Hauptverfasser: Kellam, Mark D, Bronner, Gary Bela
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Bronner, Gary Bela
description A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10614883B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10614883B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10614883B23</originalsourceid><addsrcrecordid>eNrjZBALSi3OLC5JzEtOVchNzc0vqlRITs3J4WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgZmhiYWFsZORsbEqAEAqYkhuQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Resistance memory cell</title><source>esp@cenet</source><creator>Kellam, Mark D ; Bronner, Gary Bela</creator><creatorcontrib>Kellam, Mark D ; Bronner, Gary Bela</creatorcontrib><description>A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200407&amp;DB=EPODOC&amp;CC=US&amp;NR=10614883B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200407&amp;DB=EPODOC&amp;CC=US&amp;NR=10614883B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kellam, Mark D</creatorcontrib><creatorcontrib>Bronner, Gary Bela</creatorcontrib><title>Resistance memory cell</title><description>A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBALSi3OLC5JzEtOVchNzc0vqlRITs3J4WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgZmhiYWFsZORsbEqAEAqYkhuQ</recordid><startdate>20200407</startdate><enddate>20200407</enddate><creator>Kellam, Mark D</creator><creator>Bronner, Gary Bela</creator><scope>EVB</scope></search><sort><creationdate>20200407</creationdate><title>Resistance memory cell</title><author>Kellam, Mark D ; Bronner, Gary Bela</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10614883B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Kellam, Mark D</creatorcontrib><creatorcontrib>Bronner, Gary Bela</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kellam, Mark D</au><au>Bronner, Gary Bela</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Resistance memory cell</title><date>2020-04-07</date><risdate>2020</risdate><abstract>A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
title Resistance memory cell
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-23T14%3A22%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kellam,%20Mark%20D&rft.date=2020-04-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10614883B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true