Platform debug and testing with secured hardware
A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable...
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| creator | Pappu, Lakshminarayana Dour, Navneet Cox, Christopher E |
| description | A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable testing of the connections to the memory devices. The test control circuitry is triggered separately from the other power control circuitry, and can be protected to allow only secured access for testing. |
| format | Patent |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | Platform debug and testing with secured hardware |
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