Semiconductor device and a corresponding method of manufacturing semiconductor devices

A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization...

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Hauptverfasser: Venegoni, Ivan, Colpani, Paolo, Milanesi, Francesca, Sciarrillo, Samuele
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creator Venegoni, Ivan
Colpani, Paolo
Milanesi, Francesca
Sciarrillo, Samuele
description A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10593625B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10593625B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10593625B23</originalsourceid><addsrcrecordid>eNrjZAgLTs3NTM7PSylNLskvUkhJLctMTlVIzEtRSFRIzi8qSi0uAEpm5qUr5KaWZOSnKOSnKeQm5pWmJSaXlBaBxIuxGFDMw8CalphTnMoLpbkZFN1cQ5w9dFML8uOBZiYmp-allsSHBhsamFoamxmZOhkZE6MGAIiiOps</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device and a corresponding method of manufacturing semiconductor devices</title><source>esp@cenet</source><creator>Venegoni, Ivan ; Colpani, Paolo ; Milanesi, Francesca ; Sciarrillo, Samuele</creator><creatorcontrib>Venegoni, Ivan ; Colpani, Paolo ; Milanesi, Francesca ; Sciarrillo, Samuele</creatorcontrib><description>A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200317&amp;DB=EPODOC&amp;CC=US&amp;NR=10593625B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200317&amp;DB=EPODOC&amp;CC=US&amp;NR=10593625B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Venegoni, Ivan</creatorcontrib><creatorcontrib>Colpani, Paolo</creatorcontrib><creatorcontrib>Milanesi, Francesca</creatorcontrib><creatorcontrib>Sciarrillo, Samuele</creatorcontrib><title>Semiconductor device and a corresponding method of manufacturing semiconductor devices</title><description>A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAgLTs3NTM7PSylNLskvUkhJLctMTlVIzEtRSFRIzi8qSi0uAEpm5qUr5KaWZOSnKOSnKeQm5pWmJSaXlBaBxIuxGFDMw8CalphTnMoLpbkZFN1cQ5w9dFML8uOBZiYmp-allsSHBhsamFoamxmZOhkZE6MGAIiiOps</recordid><startdate>20200317</startdate><enddate>20200317</enddate><creator>Venegoni, Ivan</creator><creator>Colpani, Paolo</creator><creator>Milanesi, Francesca</creator><creator>Sciarrillo, Samuele</creator><scope>EVB</scope></search><sort><creationdate>20200317</creationdate><title>Semiconductor device and a corresponding method of manufacturing semiconductor devices</title><author>Venegoni, Ivan ; Colpani, Paolo ; Milanesi, Francesca ; Sciarrillo, Samuele</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10593625B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Venegoni, Ivan</creatorcontrib><creatorcontrib>Colpani, Paolo</creatorcontrib><creatorcontrib>Milanesi, Francesca</creatorcontrib><creatorcontrib>Sciarrillo, Samuele</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Venegoni, Ivan</au><au>Colpani, Paolo</au><au>Milanesi, Francesca</au><au>Sciarrillo, Samuele</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device and a corresponding method of manufacturing semiconductor devices</title><date>2020-03-17</date><risdate>2020</risdate><abstract>A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor device and a corresponding method of manufacturing semiconductor devices
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T18%3A54%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Venegoni,%20Ivan&rft.date=2020-03-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10593625B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true