Managed hardware accelerator address translation fault resolution utilizing a credit

Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator pulls an operation from a first buffer and adjusts a receive credit value in a first window context operatively...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Arimilli, Lakshminarayana B, Arndt, Richard L, Blaner, Bartholomew
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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