Semiconductor device, semiconductor device manufacturing method, power supply circuit, and computer

A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer, a first and second electrode located on or above the first nitride semiconductor layer; a trench located in the secon...

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Hauptverfasser: Shimizu, Tatsuo, Yonehara, Toshiya, Mukai, Akira
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creator Shimizu, Tatsuo
Yonehara, Toshiya
Mukai, Akira
description A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer, a first and second electrode located on or above the first nitride semiconductor layer; a trench located in the second nitride semiconductor layer between the first electrode and the second electrode, and including a bottom surface and a side surface, the bottom surface being located in one of the first nitride semiconductor layer and the second nitride semiconductor layer; a gate electrode located in the trench; a gate insulating layer located between the bottom surface and the gate electrode and between the side surface and the gate electrode; and a region located in at least one of the first nitride semiconductor layer and the second nitride semiconductor layer, including a first portion adjacent to the bottom surface, and containing fluorine.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10566451B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10566451B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10566451B23</originalsourceid><addsrcrecordid>eNqNyrEKwjAQgOEuDqK-w7lHsGr7AIriXp1LuFxroMmF5E7x7V0cHZx--PjnFXYUPHJ0isIZHD09koHyQyHYqINF0ezjCIHkwc5A4hdlKJrS9Ab0GdWLARsdIIekQnlZzQY7FVp9u6jWl_PtdN1Q4p5KskiRpL939bZp20NTH3f7f54PEUw_XA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device, semiconductor device manufacturing method, power supply circuit, and computer</title><source>esp@cenet</source><creator>Shimizu, Tatsuo ; Yonehara, Toshiya ; Mukai, Akira</creator><creatorcontrib>Shimizu, Tatsuo ; Yonehara, Toshiya ; Mukai, Akira</creatorcontrib><description>A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer, a first and second electrode located on or above the first nitride semiconductor layer; a trench located in the second nitride semiconductor layer between the first electrode and the second electrode, and including a bottom surface and a side surface, the bottom surface being located in one of the first nitride semiconductor layer and the second nitride semiconductor layer; a gate electrode located in the trench; a gate insulating layer located between the bottom surface and the gate electrode and between the side surface and the gate electrode; and a region located in at least one of the first nitride semiconductor layer and the second nitride semiconductor layer, including a first portion adjacent to the bottom surface, and containing fluorine.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200218&amp;DB=EPODOC&amp;CC=US&amp;NR=10566451B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200218&amp;DB=EPODOC&amp;CC=US&amp;NR=10566451B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Shimizu, Tatsuo</creatorcontrib><creatorcontrib>Yonehara, Toshiya</creatorcontrib><creatorcontrib>Mukai, Akira</creatorcontrib><title>Semiconductor device, semiconductor device manufacturing method, power supply circuit, and computer</title><description>A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer, a first and second electrode located on or above the first nitride semiconductor layer; a trench located in the second nitride semiconductor layer between the first electrode and the second electrode, and including a bottom surface and a side surface, the bottom surface being located in one of the first nitride semiconductor layer and the second nitride semiconductor layer; a gate electrode located in the trench; a gate insulating layer located between the bottom surface and the gate electrode and between the side surface and the gate electrode; and a region located in at least one of the first nitride semiconductor layer and the second nitride semiconductor layer, including a first portion adjacent to the bottom surface, and containing fluorine.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQgOEuDqK-w7lHsGr7AIriXp1LuFxroMmF5E7x7V0cHZx--PjnFXYUPHJ0isIZHD09koHyQyHYqINF0ezjCIHkwc5A4hdlKJrS9Ab0GdWLARsdIIekQnlZzQY7FVp9u6jWl_PtdN1Q4p5KskiRpL939bZp20NTH3f7f54PEUw_XA</recordid><startdate>20200218</startdate><enddate>20200218</enddate><creator>Shimizu, Tatsuo</creator><creator>Yonehara, Toshiya</creator><creator>Mukai, Akira</creator><scope>EVB</scope></search><sort><creationdate>20200218</creationdate><title>Semiconductor device, semiconductor device manufacturing method, power supply circuit, and computer</title><author>Shimizu, Tatsuo ; Yonehara, Toshiya ; Mukai, Akira</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10566451B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Shimizu, Tatsuo</creatorcontrib><creatorcontrib>Yonehara, Toshiya</creatorcontrib><creatorcontrib>Mukai, Akira</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shimizu, Tatsuo</au><au>Yonehara, Toshiya</au><au>Mukai, Akira</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device, semiconductor device manufacturing method, power supply circuit, and computer</title><date>2020-02-18</date><risdate>2020</risdate><abstract>A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer, a first and second electrode located on or above the first nitride semiconductor layer; a trench located in the second nitride semiconductor layer between the first electrode and the second electrode, and including a bottom surface and a side surface, the bottom surface being located in one of the first nitride semiconductor layer and the second nitride semiconductor layer; a gate electrode located in the trench; a gate insulating layer located between the bottom surface and the gate electrode and between the side surface and the gate electrode; and a region located in at least one of the first nitride semiconductor layer and the second nitride semiconductor layer, including a first portion adjacent to the bottom surface, and containing fluorine.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor device, semiconductor device manufacturing method, power supply circuit, and computer
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T07%3A22%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Shimizu,%20Tatsuo&rft.date=2020-02-18&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10566451B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true