Power semiconductor device and method for manufacturing the same
A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and...
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| creator | Cho, Jun Hee Chung, Jin Seong Lee, Tae Hoon |
| description | A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10566422B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10566422B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10566422B23</originalsourceid><addsrcrecordid>eNrjZHAIyC9PLVIoTs3NTM7PSylNLskvUkhJLctMTlVIzEtRyE0tychPUUgDiuYm5pWmJSaXlBZl5qUrlGSkKhQn5qbyMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjU4oLE5NS81JL40GBDA1MzMxMjIycjY2LUAADsfDGh</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Power semiconductor device and method for manufacturing the same</title><source>esp@cenet</source><creator>Cho, Jun Hee ; Chung, Jin Seong ; Lee, Tae Hoon</creator><creatorcontrib>Cho, Jun Hee ; Chung, Jin Seong ; Lee, Tae Hoon</creatorcontrib><description>A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200218&DB=EPODOC&CC=US&NR=10566422B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200218&DB=EPODOC&CC=US&NR=10566422B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Cho, Jun Hee</creatorcontrib><creatorcontrib>Chung, Jin Seong</creatorcontrib><creatorcontrib>Lee, Tae Hoon</creatorcontrib><title>Power semiconductor device and method for manufacturing the same</title><description>A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAIyC9PLVIoTs3NTM7PSylNLskvUkhJLctMTlVIzEtRyE0tychPUUgDiuYm5pWmJSaXlBZl5qUrlGSkKhQn5qbyMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjU4oLE5NS81JL40GBDA1MzMxMjIycjY2LUAADsfDGh</recordid><startdate>20200218</startdate><enddate>20200218</enddate><creator>Cho, Jun Hee</creator><creator>Chung, Jin Seong</creator><creator>Lee, Tae Hoon</creator><scope>EVB</scope></search><sort><creationdate>20200218</creationdate><title>Power semiconductor device and method for manufacturing the same</title><author>Cho, Jun Hee ; Chung, Jin Seong ; Lee, Tae Hoon</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10566422B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Cho, Jun Hee</creatorcontrib><creatorcontrib>Chung, Jin Seong</creatorcontrib><creatorcontrib>Lee, Tae Hoon</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cho, Jun Hee</au><au>Chung, Jin Seong</au><au>Lee, Tae Hoon</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Power semiconductor device and method for manufacturing the same</title><date>2020-02-18</date><risdate>2020</risdate><abstract>A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Power semiconductor device and method for manufacturing the same |
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