Integrated circuit structures comprising conductive vias and methods of forming conductive vias

Integrated circuit structures comprising conductive vias and methods of forming conductive vias

A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via openin...

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1. Verfasser: Liu, Zengtao T
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Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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description A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance. Integrated circuit structure comprising conductive vias independent of method of manufacture are disclosed.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10559531B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10559531B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10559531B23</originalsourceid><addsrcrecordid>eNqNirsKAjEQANNYiPoP6wcInkcKW0XRWq1DSDZ3C-ZBdnPf7xWWFlYzDLNU5p4Eh2oFPTiqrpEAS21OWkUGl2OpxJSGWZOfM00IE1kGmzxElDF7hhwg5Bp_bGu1CPbNuPlypbbXy_N822HJBrlYhwnFvB7dXuuj7rvTof_n-QAidD4p</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit structures comprising conductive vias and methods of forming conductive vias</title><source>esp@cenet</source><creator>Liu, Zengtao T</creator><creatorcontrib>Liu, Zengtao T</creatorcontrib><description>A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance. Integrated circuit structure comprising conductive vias independent of method of manufacture are disclosed.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200211&amp;DB=EPODOC&amp;CC=US&amp;NR=10559531B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200211&amp;DB=EPODOC&amp;CC=US&amp;NR=10559531B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Liu, Zengtao T</creatorcontrib><title>Integrated circuit structures comprising conductive vias and methods of forming conductive vias</title><description>A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance. Integrated circuit structure comprising conductive vias independent of method of manufacture are disclosed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNirsKAjEQANNYiPoP6wcInkcKW0XRWq1DSDZ3C-ZBdnPf7xWWFlYzDLNU5p4Eh2oFPTiqrpEAS21OWkUGl2OpxJSGWZOfM00IE1kGmzxElDF7hhwg5Bp_bGu1CPbNuPlypbbXy_N822HJBrlYhwnFvB7dXuuj7rvTof_n-QAidD4p</recordid><startdate>20200211</startdate><enddate>20200211</enddate><creator>Liu, Zengtao T</creator><scope>EVB</scope></search><sort><creationdate>20200211</creationdate><title>Integrated circuit structures comprising conductive vias and methods of forming conductive vias</title><author>Liu, Zengtao T</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10559531B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Liu, Zengtao T</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Liu, Zengtao T</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit structures comprising conductive vias and methods of forming conductive vias</title><date>2020-02-11</date><risdate>2020</risdate><abstract>A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance. Integrated circuit structure comprising conductive vias independent of method of manufacture are disclosed.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Integrated circuit structures comprising conductive vias and methods of forming conductive vias
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-25T14%3A31%3A34IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Liu,%20Zengtao%20T&rft.date=2020-02-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10559531B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true