System, apparatus and method for simultaneous read and precharge of a memory

In one embodiment, an apparatus includes a memory array having a plurality of memory cells, a plurality of bitlines coupled to the plurality of memory cells, and a plurality of wordlines coupled to the plurality of memory cells. The memory array may further include a sense amplifier circuit to sense and amplify a value stored in a memory cell of the plurality of memory cells. The sense amplifier circuit may include: a buffer circuit to store the value, the buffer circuit coupled between a first internal node of the sense amplifier circuit and a second internal node of the sense amplifier circuit; and an equalization circuit to equalize the first internal node and the second internal node while the sense amplifier circuit is decoupled from the memory array. Other embodiments are described and claimed.