Gate driver and display device having the same
A display device comprises a pixel array, a timing controller, a Q node control signal input line, and a shift register. In the pixel array, data lines and gate lines are defined, and pixels are arranged in a matrix. The timing controller outputs a start signal and a first reset signal. The Q node c...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Jang, Hyunguk Heo, Seungho |
description | A display device comprises a pixel array, a timing controller, a Q node control signal input line, and a shift register. In the pixel array, data lines and gate lines are defined, and pixels are arranged in a matrix. The timing controller outputs a start signal and a first reset signal. The Q node control signal input line receives the start signal and the first reset signal. The shift register comprises a plurality of stages connected as a cascade, and sequentially supplies dummy gate pulses or gate pulses applied to the gate lines. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10553147B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10553147B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10553147B23</originalsourceid><addsrcrecordid>eNrjZNBzTyxJVUgpyixLLVJIzEtRSMksLshJrFRISS3LTE5VyEgsy8xLVyjJSFUoTsxN5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgampsaGJuZORsbEqAEAwlQqJw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Gate driver and display device having the same</title><source>esp@cenet</source><creator>Jang, Hyunguk ; Heo, Seungho</creator><creatorcontrib>Jang, Hyunguk ; Heo, Seungho</creatorcontrib><description>A display device comprises a pixel array, a timing controller, a Q node control signal input line, and a shift register. In the pixel array, data lines and gate lines are defined, and pixels are arranged in a matrix. The timing controller outputs a start signal and a first reset signal. The Q node control signal input line receives the start signal and the first reset signal. The shift register comprises a plurality of stages connected as a cascade, and sequentially supplies dummy gate pulses or gate pulses applied to the gate lines.</description><language>eng</language><subject>ADVERTISING ; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION ; CRYPTOGRAPHY ; DISPLAY ; EDUCATION ; INFORMATION STORAGE ; PHYSICS ; SEALS ; STATIC STORES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200204&DB=EPODOC&CC=US&NR=10553147B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200204&DB=EPODOC&CC=US&NR=10553147B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Jang, Hyunguk</creatorcontrib><creatorcontrib>Heo, Seungho</creatorcontrib><title>Gate driver and display device having the same</title><description>A display device comprises a pixel array, a timing controller, a Q node control signal input line, and a shift register. In the pixel array, data lines and gate lines are defined, and pixels are arranged in a matrix. The timing controller outputs a start signal and a first reset signal. The Q node control signal input line receives the start signal and the first reset signal. The shift register comprises a plurality of stages connected as a cascade, and sequentially supplies dummy gate pulses or gate pulses applied to the gate lines.</description><subject>ADVERTISING</subject><subject>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</subject><subject>CRYPTOGRAPHY</subject><subject>DISPLAY</subject><subject>EDUCATION</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEALS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNBzTyxJVUgpyixLLVJIzEtRSMksLshJrFRISS3LTE5VyEgsy8xLVyjJSFUoTsxN5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgampsaGJuZORsbEqAEAwlQqJw</recordid><startdate>20200204</startdate><enddate>20200204</enddate><creator>Jang, Hyunguk</creator><creator>Heo, Seungho</creator><scope>EVB</scope></search><sort><creationdate>20200204</creationdate><title>Gate driver and display device having the same</title><author>Jang, Hyunguk ; Heo, Seungho</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10553147B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>ADVERTISING</topic><topic>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</topic><topic>CRYPTOGRAPHY</topic><topic>DISPLAY</topic><topic>EDUCATION</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEALS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Jang, Hyunguk</creatorcontrib><creatorcontrib>Heo, Seungho</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jang, Hyunguk</au><au>Heo, Seungho</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Gate driver and display device having the same</title><date>2020-02-04</date><risdate>2020</risdate><abstract>A display device comprises a pixel array, a timing controller, a Q node control signal input line, and a shift register. In the pixel array, data lines and gate lines are defined, and pixels are arranged in a matrix. The timing controller outputs a start signal and a first reset signal. The Q node control signal input line receives the start signal and the first reset signal. The shift register comprises a plurality of stages connected as a cascade, and sequentially supplies dummy gate pulses or gate pulses applied to the gate lines.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US10553147B2 |
source | esp@cenet |
subjects | ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CRYPTOGRAPHY DISPLAY EDUCATION INFORMATION STORAGE PHYSICS SEALS STATIC STORES |
title | Gate driver and display device having the same |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T03%3A30%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Jang,%20Hyunguk&rft.date=2020-02-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10553147B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |