Glitch-aware phase algebra for clock analysis
In some embodiments, a method for processing register transfer level code representing a circuit design. The method can include determining, by one or more processors based on the register transfer level code, an input sequence of signal transitions associated with an input net of a component repres...
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| creator | Drasny, Gabor Meil, Gavin B |
| description | In some embodiments, a method for processing register transfer level code representing a circuit design. The method can include determining, by one or more processors based on the register transfer level code, an input sequence of signal transitions associated with an input net of a component represented in the register transfer level code, wherein each signal transition represents a nondeterministic transition from a first signal state to one or more possible signal states; determining, at least one of the processors based on the register transfer level code, that a subsequence of signal transitions of the input sequence indicates at most one transition within the subsequence; and determining, by at least one of the processors based on the component represented in the register transfer level code and on the subsequence, an output sequence of signal transitions derived from the input sequence of signal transition. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10552559B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10552559B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10552559B23</originalsourceid><addsrcrecordid>eNrjZNB1z8ksSc7QTSxPLEpVKMhILE5VSMxJT00qSlRIyy9SSM7JT85WSMxLzKkszizmYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGBqamRqamlk5GxsSoAQCqrioW</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Glitch-aware phase algebra for clock analysis</title><source>esp@cenet</source><creator>Drasny, Gabor ; Meil, Gavin B</creator><creatorcontrib>Drasny, Gabor ; Meil, Gavin B</creatorcontrib><description>In some embodiments, a method for processing register transfer level code representing a circuit design. The method can include determining, by one or more processors based on the register transfer level code, an input sequence of signal transitions associated with an input net of a component represented in the register transfer level code, wherein each signal transition represents a nondeterministic transition from a first signal state to one or more possible signal states; determining, at least one of the processors based on the register transfer level code, that a subsequence of signal transitions of the input sequence indicates at most one transition within the subsequence; and determining, by at least one of the processors based on the component represented in the register transfer level code and on the subsequence, an output sequence of signal transitions derived from the input sequence of signal transition.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200204&DB=EPODOC&CC=US&NR=10552559B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200204&DB=EPODOC&CC=US&NR=10552559B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Drasny, Gabor</creatorcontrib><creatorcontrib>Meil, Gavin B</creatorcontrib><title>Glitch-aware phase algebra for clock analysis</title><description>In some embodiments, a method for processing register transfer level code representing a circuit design. The method can include determining, by one or more processors based on the register transfer level code, an input sequence of signal transitions associated with an input net of a component represented in the register transfer level code, wherein each signal transition represents a nondeterministic transition from a first signal state to one or more possible signal states; determining, at least one of the processors based on the register transfer level code, that a subsequence of signal transitions of the input sequence indicates at most one transition within the subsequence; and determining, by at least one of the processors based on the component represented in the register transfer level code and on the subsequence, an output sequence of signal transitions derived from the input sequence of signal transition.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNB1z8ksSc7QTSxPLEpVKMhILE5VSMxJT00qSlRIyy9SSM7JT85WSMxLzKkszizmYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGBqamRqamlk5GxsSoAQCqrioW</recordid><startdate>20200204</startdate><enddate>20200204</enddate><creator>Drasny, Gabor</creator><creator>Meil, Gavin B</creator><scope>EVB</scope></search><sort><creationdate>20200204</creationdate><title>Glitch-aware phase algebra for clock analysis</title><author>Drasny, Gabor ; Meil, Gavin B</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10552559B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Drasny, Gabor</creatorcontrib><creatorcontrib>Meil, Gavin B</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Drasny, Gabor</au><au>Meil, Gavin B</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Glitch-aware phase algebra for clock analysis</title><date>2020-02-04</date><risdate>2020</risdate><abstract>In some embodiments, a method for processing register transfer level code representing a circuit design. The method can include determining, by one or more processors based on the register transfer level code, an input sequence of signal transitions associated with an input net of a component represented in the register transfer level code, wherein each signal transition represents a nondeterministic transition from a first signal state to one or more possible signal states; determining, at least one of the processors based on the register transfer level code, that a subsequence of signal transitions of the input sequence indicates at most one transition within the subsequence; and determining, by at least one of the processors based on the component represented in the register transfer level code and on the subsequence, an output sequence of signal transitions derived from the input sequence of signal transition.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Glitch-aware phase algebra for clock analysis |
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