Method and apparatus for supporting the use of interleaved memory regions

Method and apparatus for supporting the use of interleaved memory regions

A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respecti...

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Hauptverfasser: Guarnaccia, Giuseppe, Soulie, Michael, Catalano, Valerio, Maruccia, Giuseppe, Guarrasi, Raffaele, Locatelli, Riccardo
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator Guarnaccia, Giuseppe
Soulie, Michael
Catalano, Valerio
Maruccia, Giuseppe
Guarrasi, Raffaele
Locatelli, Riccardo
description A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10540277B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10540277B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10540277B23</originalsourceid><addsrcrecordid>eNqNyjEKwkAQRuE0FqLeYTyAEKOSXlG0sFLrsJh_k4VkZ5mZFby9Fh7A4vE1b1pcrrCeW3LxW0pOnGUlz0KaU2KxEDuyHpQVxJ5CNMgA90JLI0aWNwm6wFHnxcS7QbH4OSuWp-P9cF4hcQNN7okIax63dbnbllVd76vNP88HBZQ1JQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for supporting the use of interleaved memory regions</title><source>esp@cenet</source><creator>Guarnaccia, Giuseppe ; Soulie, Michael ; Catalano, Valerio ; Maruccia, Giuseppe ; Guarrasi, Raffaele ; Locatelli, Riccardo</creator><creatorcontrib>Guarnaccia, Giuseppe ; Soulie, Michael ; Catalano, Valerio ; Maruccia, Giuseppe ; Guarrasi, Raffaele ; Locatelli, Riccardo</creatorcontrib><description>A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200121&amp;DB=EPODOC&amp;CC=US&amp;NR=10540277B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200121&amp;DB=EPODOC&amp;CC=US&amp;NR=10540277B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Guarnaccia, Giuseppe</creatorcontrib><creatorcontrib>Soulie, Michael</creatorcontrib><creatorcontrib>Catalano, Valerio</creatorcontrib><creatorcontrib>Maruccia, Giuseppe</creatorcontrib><creatorcontrib>Guarrasi, Raffaele</creatorcontrib><creatorcontrib>Locatelli, Riccardo</creatorcontrib><title>Method and apparatus for supporting the use of interleaved memory regions</title><description>A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEKwkAQRuE0FqLeYTyAEKOSXlG0sFLrsJh_k4VkZ5mZFby9Fh7A4vE1b1pcrrCeW3LxW0pOnGUlz0KaU2KxEDuyHpQVxJ5CNMgA90JLI0aWNwm6wFHnxcS7QbH4OSuWp-P9cF4hcQNN7okIax63dbnbllVd76vNP88HBZQ1JQ</recordid><startdate>20200121</startdate><enddate>20200121</enddate><creator>Guarnaccia, Giuseppe</creator><creator>Soulie, Michael</creator><creator>Catalano, Valerio</creator><creator>Maruccia, Giuseppe</creator><creator>Guarrasi, Raffaele</creator><creator>Locatelli, Riccardo</creator><scope>EVB</scope></search><sort><creationdate>20200121</creationdate><title>Method and apparatus for supporting the use of interleaved memory regions</title><author>Guarnaccia, Giuseppe ; Soulie, Michael ; Catalano, Valerio ; Maruccia, Giuseppe ; Guarrasi, Raffaele ; Locatelli, Riccardo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10540277B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Guarnaccia, Giuseppe</creatorcontrib><creatorcontrib>Soulie, Michael</creatorcontrib><creatorcontrib>Catalano, Valerio</creatorcontrib><creatorcontrib>Maruccia, Giuseppe</creatorcontrib><creatorcontrib>Guarrasi, Raffaele</creatorcontrib><creatorcontrib>Locatelli, Riccardo</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Guarnaccia, Giuseppe</au><au>Soulie, Michael</au><au>Catalano, Valerio</au><au>Maruccia, Giuseppe</au><au>Guarrasi, Raffaele</au><au>Locatelli, Riccardo</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for supporting the use of interleaved memory regions</title><date>2020-01-21</date><risdate>2020</risdate><abstract>A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Method and apparatus for supporting the use of interleaved memory regions
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T06%3A02%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Guarnaccia,%20Giuseppe&rft.date=2020-01-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10540277B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true