Method and apparatus of operating synchronizing high-speed clock dividers to correct clock skew

A synchronizing high-speed clock divider has a Clk input, a Clks input, and a reset input configured to correct phase misalignment on clock divider outputs caused by phase skew between a Clk input signal and a Clks input signal, and comprises a reset synchronizer configured to generate at least one...

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Bibliographische Detailangaben

Hauptverfasser:	Chalasani, Prasad, Quan, Shaolei, Gadde, Vijay
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
Online-Zugang:	Volltext bestellen
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