Memory control circuit, memory, and memory control method

A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value dif...

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Hauptverfasser: Maeda, Masazumi, Ise, Masahiro
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creator Maeda, Masazumi
Ise, Masahiro
description A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10497445B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10497445B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10497445B23</originalsourceid><addsrcrecordid>eNrjZLD0Tc3NL6pUSM7PKynKz1FIzixKLs0s0VHIBYvrKCTmpUDZcDW5qSUZ-Sk8DKxpiTnFqbxQmptB0c01xNlDN7UgPz61uCAxOTUvtSQ-NNjQwMTS3MTE1MnImBg1AEebLuQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Memory control circuit, memory, and memory control method</title><source>esp@cenet</source><creator>Maeda, Masazumi ; Ise, Masahiro</creator><creatorcontrib>Maeda, Masazumi ; Ise, Masahiro</creatorcontrib><description>A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20191203&amp;DB=EPODOC&amp;CC=US&amp;NR=10497445B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20191203&amp;DB=EPODOC&amp;CC=US&amp;NR=10497445B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Maeda, Masazumi</creatorcontrib><creatorcontrib>Ise, Masahiro</creatorcontrib><title>Memory control circuit, memory, and memory control method</title><description>A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD0Tc3NL6pUSM7PKynKz1FIzixKLs0s0VHIBYvrKCTmpUDZcDW5qSUZ-Sk8DKxpiTnFqbxQmptB0c01xNlDN7UgPz61uCAxOTUvtSQ-NNjQwMTS3MTE1MnImBg1AEebLuQ</recordid><startdate>20191203</startdate><enddate>20191203</enddate><creator>Maeda, Masazumi</creator><creator>Ise, Masahiro</creator><scope>EVB</scope></search><sort><creationdate>20191203</creationdate><title>Memory control circuit, memory, and memory control method</title><author>Maeda, Masazumi ; Ise, Masahiro</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10497445B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Maeda, Masazumi</creatorcontrib><creatorcontrib>Ise, Masahiro</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Maeda, Masazumi</au><au>Ise, Masahiro</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Memory control circuit, memory, and memory control method</title><date>2019-12-03</date><risdate>2019</risdate><abstract>A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage.</abstract><oa>free_for_read</oa></addata></record>
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STATIC STORES
title Memory control circuit, memory, and memory control method
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T17%3A31%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Maeda,%20Masazumi&rft.date=2019-12-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10497445B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true