Vertically stacked multichip modules
In a general aspect, a circuit assembly apparatus can include first and second semiconductor die, and a substrate. The substrate can include an insulating layer; a first metal layer disposed on a first side of the insulating layer, a first side of the first semiconductor die disposed on and electric...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Jong, Mankyo Park, Changyoung |
description | In a general aspect, a circuit assembly apparatus can include first and second semiconductor die, and a substrate. The substrate can include an insulating layer; a first metal layer disposed on a first side of the insulating layer, a first side of the first semiconductor die disposed on and electrically coupled with the first metal layer; a second metal layer disposed on a second side of the insulating layer, the second side of the insulating layer being opposite the first side of the insulating layer, a first side of the second semiconductor die being disposed on and electrically coupled with the second metal layer; and a conductive via disposed through the insulating layer, the conductive via electrically coupling the first metal layer with the second metal layer, the first metal layer, the conductive via and the second metal layer electrically coupling the first semiconductor die with the second semiconductor die. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10483237B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10483237B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10483237B23</originalsourceid><addsrcrecordid>eNrjZFAJSy0qyUxOzMmpVCguSUzOTk1RyC3NAQplZBYo5OanlOakFvMwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUkvjQYEMDEwtjI2NzJyNjYtQAAEE2J10</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Vertically stacked multichip modules</title><source>esp@cenet</source><creator>Jong, Mankyo ; Park, Changyoung</creator><creatorcontrib>Jong, Mankyo ; Park, Changyoung</creatorcontrib><description>In a general aspect, a circuit assembly apparatus can include first and second semiconductor die, and a substrate. The substrate can include an insulating layer; a first metal layer disposed on a first side of the insulating layer, a first side of the first semiconductor die disposed on and electrically coupled with the first metal layer; a second metal layer disposed on a second side of the insulating layer, the second side of the insulating layer being opposite the first side of the insulating layer, a first side of the second semiconductor die being disposed on and electrically coupled with the second metal layer; and a conductive via disposed through the insulating layer, the conductive via electrically coupling the first metal layer with the second metal layer, the first metal layer, the conductive via and the second metal layer electrically coupling the first semiconductor die with the second semiconductor die.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20191119&DB=EPODOC&CC=US&NR=10483237B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20191119&DB=EPODOC&CC=US&NR=10483237B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Jong, Mankyo</creatorcontrib><creatorcontrib>Park, Changyoung</creatorcontrib><title>Vertically stacked multichip modules</title><description>In a general aspect, a circuit assembly apparatus can include first and second semiconductor die, and a substrate. The substrate can include an insulating layer; a first metal layer disposed on a first side of the insulating layer, a first side of the first semiconductor die disposed on and electrically coupled with the first metal layer; a second metal layer disposed on a second side of the insulating layer, the second side of the insulating layer being opposite the first side of the insulating layer, a first side of the second semiconductor die being disposed on and electrically coupled with the second metal layer; and a conductive via disposed through the insulating layer, the conductive via electrically coupling the first metal layer with the second metal layer, the first metal layer, the conductive via and the second metal layer electrically coupling the first semiconductor die with the second semiconductor die.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAJSy0qyUxOzMmpVCguSUzOTk1RyC3NAQplZBYo5OanlOakFvMwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUkvjQYEMDEwtjI2NzJyNjYtQAAEE2J10</recordid><startdate>20191119</startdate><enddate>20191119</enddate><creator>Jong, Mankyo</creator><creator>Park, Changyoung</creator><scope>EVB</scope></search><sort><creationdate>20191119</creationdate><title>Vertically stacked multichip modules</title><author>Jong, Mankyo ; Park, Changyoung</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10483237B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Jong, Mankyo</creatorcontrib><creatorcontrib>Park, Changyoung</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jong, Mankyo</au><au>Park, Changyoung</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Vertically stacked multichip modules</title><date>2019-11-19</date><risdate>2019</risdate><abstract>In a general aspect, a circuit assembly apparatus can include first and second semiconductor die, and a substrate. The substrate can include an insulating layer; a first metal layer disposed on a first side of the insulating layer, a first side of the first semiconductor die disposed on and electrically coupled with the first metal layer; a second metal layer disposed on a second side of the insulating layer, the second side of the insulating layer being opposite the first side of the insulating layer, a first side of the second semiconductor die being disposed on and electrically coupled with the second metal layer; and a conductive via disposed through the insulating layer, the conductive via electrically coupling the first metal layer with the second metal layer, the first metal layer, the conductive via and the second metal layer electrically coupling the first semiconductor die with the second semiconductor die.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US10483237B2 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Vertically stacked multichip modules |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-26T07%3A49%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Jong,%20Mankyo&rft.date=2019-11-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10483237B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |