Flash memory cell with dual erase modes for increased cell endurance

An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and ther...

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Bibliographische Detailangaben

Hauptverfasser:	Reboulet, Luc, Walls, James
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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